Senior IP Design Engineer

OMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD.; Singapore; On-site; SGD 80,000 - 110,000; Full time

Job summary

A leading technology company in Singapore is looking for a digital design engineer to join their dynamic team. The successful candidate will develop advanced digital processing engines and contribute to the microarchitecture design. Candidates must have at least 5 years of hands-on experience in digital design and a strong background in Verilog/SystemVerilog, with solid knowledge of bus protocols. This role emphasizes teamwork and effective communication skills.

Qualifications

• 5+ years of hands-on digital design experience.
• Experience in IP architecture/micro-architecture and design.
• Experience in multiple clock domain, power domain design.

Responsibilities

• Develop design requirements from system level specifications.
• Microarchitecture design and RTL coding using Verilog/SystemVerilog HDL.
• Estimate, measure and optimize PPA (Performance/Power/Area).

Skills

Digital design experience

Verilog/SystemVerilog

System-level specifications

Communication skills

Team collaboration

Education

MSEE/BSEE in Electrical Engineering or Computer Engineering

Tools

AXI/AHB/APB bus protocol

UVM verification methodology

Job description

Description

• You would be part of a dynamic digital IP design team that develops state-of-the-art video processing engines, neural processing units, advanced video analytics accelerators, etc.

Responsibilities

• Develop design requirements from a given system level specifications.
• Microarchitecture design and RTL coding using Verilog / SystemVerilog HDL.
• Create and maintain module level functional tests
• Estimate, measure and optimize PPA (Performance / Power / Area) to meet key objectives and results.
• Work closely with verification engineers to ensure comprehensive testing and debug issues, especially at system level.
• Support integration into the overall system, conducting design checks, and addressing lint/timing/CDC issues.

Requirements

• MSEE/BSEE in Electrical Engineering or Computer Engineering.
• 5+ years of hangs-on digital design experience.
• Experience in IP architecture/micro-architecture and design, and RTL coding with Verilog/SystemVerilog
• Experience in AXI/AHB/APB bus protocol
• Experience in multiple clock domain, power domain design
• Experience in synthesis, with analysis of power, timing and area.
• Experience in UVM verification methodology is a plus
• Experience with ARM or RISC-V processor systems is a plus.
• Disciplined, quality-minded, and highly driven for excellence.
• Excellent team player and good communication skills.