Senior Silicon Design Engineer

XILINX ASIA PACIFIC PTE. LTD.; Singapore; On-site; SGD 70,000 - 100,000; Full time

Job summary

A leading technology firm in Singapore seeks a physical design engineer to focus on ASIC development. Responsibilities include implementing DFT processes and working with various design teams. Candidates should have strong communication skills, analytical capabilities, and a degree in Computer/Electrical Engineering. Proficiency in programming languages and EDA tools is a must. This role promises a collaborative environment and innovative challenges.

Qualifications

• Strong analytical and problem-solving skills.
• Experience collaborating with engineers across different sites/timezones.
• Passion for modern physical design in digital engineering.

Responsibilities

• Develop and implement plans for DFT and timing closure on digital integrated circuits.
• Work with various design groups to meet timing, area, power, and performance requirements.
• Maintain synthesis and STA scripts using best methodologies.
• Analyze log and report files for required results adjustments.
• Regularly communicate with worldwide project teams.
• Propose enhancements to synthesis and DFT methodologies.

Skills

Analytical skills

Problem-solving skills

Communication skills

Team collaboration

Education

Bachelor's or Master's degree in Computer Engineering/Electrical Engineering

Tools

Verilog

System Verilog

C

C++

Linux

Windows

Perl

TCL

Makefile

Shell scripting

Job description

THE ROLE:

The focus of this role is to plan, build, and execute the physical design of new and existing features for AMD’s IP, resulting in quality database for the final deliveries.

THE PERSON:

You have a passion for modern, complex physical design aspects of digital design. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

• Develop and implement plans to synthesize, implement Design-For-Test (DFT) and close timing on complex digital integrated circuits.
• Work with various design groups across different disciplines (Logic, Circuits, DFT & Layout) to meet timing closure, area, power, and performance requirements.
• Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.
• Analyze log and report files to ensure the tools are getting the required results and make adjustments to the scripts to get the required results within the scheduled milestones.
• Communicate regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule.
• Provide/propose new/enhance synthesis, DFT and STA flow and methodology to reduce the development TAT to meet product requirements.

PREFERRED EXPERIENCE:

• Proficient in IP level ASIC physical design including hierarchical implementation
• Proficient in using physical design RTL2GDS EDA tools and working in Linux and Windows environments
• Experienced with Verilog, System Verilog, C, and C++
• Automating workflows in a distributed compute environment.
• Good understanding and hands-on experience in timing constraints development
• Scripting language experience: Perl, TCL, Makefile, shell preferred.
• Exposure to leadership or mentorship is an asset

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in Computer Engineering/Electrical Engineering

LOCATION:

Singapore