Senior Flip-Chip BGA Package Design Engineer

Avago Technologies Intl' Sales Pte Ltd; Singapore; On-site; SGD 90,000 - 180,000; Full time

Job summary

Broadcom is seeking an experienced package design engineer for complex flip-chip-BGA packages used in high-performance ASICs, with SerDes at 200G and above and RF/microwave ADC/DAC technologies. You will join a global R&D team developing package designs for AI, networking, HPC, and 5G base stations.

Responsibilities include overall design and routing, impedance matching, and ensuring signal/power integrity across multiple projects, with collaboration across internal teams and external vendors.

Qualifications

• B.Eng in EE/EEE with 5+ years in flip-chip-BGA package design including high-speed SerDes.
• M.Eng in EE/EEE with 3+ years in flip-chip-BGA package design including high-speed SerDes.
• Knowledge of package-level signal integrity and power integrity.
• Cadence APD experience preferred; equivalent tools considered.
• Collaborate with worldwide team across multiple time zones.
• Strong organizational and project-management skills.

Responsibilities

• Overall design responsibility for ASIC package designs (layout/routing) including impedance matching, crosstalk, signal integrity, power integrity, manufacturability, reliability, and thermal.
• Package design of high-frequency/high-data-rate structures for SerDes, ADC/DAC, DDR, HBM, etc.
• Schedule, prioritize, and track work across multiple projects.
• General flip-chip BGA package design and engineering.

Skills

High-speed SerDes

Signal integrity

Power integrity

Project coordination

Education

B.Eng in EE/EEE

M.Eng in EE/EEE

Tools

Cadence APD

Allegro

Job description

Broadcom is seeking an experienced package design engineer for complex flip-chip-BGA packages used in high-performance ASICs, with SerDes at 200G and above and RF/microwave ADC/DAC technologies. You will join a global R&D team developing package designs for AI, networking, HPC, and 5G base stations.

Responsibilities include overall design and routing, impedance matching, and ensuring signal/power integrity across multiple projects, with collaboration across internal teams and external vendors.