Flip-Chip BGA Package Design Engineer - High-Speed SerDes

Broadcom; Singapore; On-site; SGD 130,000 - 190,000; Full time

Job summary

Broadcom is seeking an experienced package design engineer to design complex flip-chip-BGA packages for ASICs with high-speed SerDes and RF/microwave ADC/DAC. You will join a global R&D team developing high-performance package designs for ASICs used in AI, networking, HPC, and 5G base stations, including 200G SerDes and higher.

Responsibilities include end-to-end package design, impedance/power integrity, and collaboration with internal and external teams.

Qualifications

• B.Eng (EE/EEE) or similar required.
• M.Eng (EE/EEE) or similar required.
• Knowledge of package-level signal integrity and power integrity.
• Cadence APD (Allegro package designer) experience preferred; other tools considered.

Responsibilities

• Overall design responsibility for ASIC package designs (layout/routing), including impedance matching, crosstalk, signal integrity, power integrity, manufacturability, reliability and thermal, in partnership with our package engineering experts.
• Package design of critical high frequency/datarate structures for SerDes, ADC/DAC, DDR, HBM, etc.
• Schedule, prioritize, & track your work across multiple projects simultaneously
• General flip-chip BGA package design & engineering

Skills

Signal integrity

Cross-team collaboration

Time management

Education

B.Eng (EE/EEE) or similar

M.Eng (EE/EEE) or similar

Tools

Cadence APD (Allegro)

Job description

Broadcom is seeking an experienced package design engineer to design complex flip-chip-BGA packages for ASICs with high-speed SerDes and RF/microwave ADC/DAC. You will join a global R&D team developing high-performance package designs for ASICs used in AI, networking, HPC, and 5G base stations, including 200G SerDes and higher.

Responsibilities include end-to-end package design, impedance/power integrity, and collaboration with internal and external teams.