Senior I/O & Analog IC Design Engineer

Broadcom Inc.; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Broadcom Inc. is seeking an I/O Design Engineer for its Central Engineering Group. The role focuses on analog and mixed-signal IC design, contributing to IP and I/O design, and collaborating across fabrication and test activities.

The candidate will run simulations, oversee RTL/physical design interactions, and develop models and documentation for integration into broad AI-related programs on advanced nodes, with growth opportunities within a world-class team.

Qualifications

• MS or PhD in Electrical Engineering.
• 6+ years of I/O or analog circuit design experience.
• Deep proficiency in Cadence Virtuoso Schematic/Layout capture and SPICE/Spectre circuit simulation.
• Solid foundation in I/O protocols including GPIO, I2C, I3C, eMMC, RGMII and SPMI.
• Familiarity with ESD, EMI and Signal Integrity.
• Experience with advanced CMOS FinFET and GAA process nodes, including features, technology limitations and PPA tradeoffs.

Responsibilities

• Design of CMOS I/O, high-precision bandgap references, op-amps, comparators and power-on-reset circuits.
• Run simulations to validate AC/DC performance, signal integrity, jitter and power.
• Perform transistor reliability and EMIR analysis.
• Work closely with layout teams to oversee physical design and verification.
• Build Verilog, Synopsys Liberty and IBIS models.
• Create and maintain detailed technical documentation, including datasheets, application notes and integration guides.
• Support chip-level integration and silicon bring-up in test chips and customer products.

Skills

Analog IC design

I/O design

Mixed-signal expertise

I/O protocol knowledge (GPIO, I2C, I3C

Signal integrity

Education

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Virtuoso

SPICE/Spectre

Verilog

IBIS modelling

Job description

Broadcom Inc. is seeking an I/O Design Engineer for its Central Engineering Group. The role focuses on analog and mixed-signal IC design, contributing to IP and I/O design, and collaborating across fabrication and test activities.

The candidate will run simulations, oversee RTL/physical design interactions, and develop models and documentation for integration into broad AI-related programs on advanced nodes, with growth opportunities within a world-class team.