Senior Flip-Chip BGA Package Design Engineer (SerDes)

Broadcom Inc.; Singapore; On-site; SGD 150,000 - 210,000; Full time

Job summary

Broadcom Inc. is seeking an experienced package design engineer to develop complex flip-chip-BGA packages for ASICs used in AI, networking, HPC, and 5G.

You will help enable high-performance SerDes at 200G and above, RF/microwave ADC/DAC, DDR, and HBM through careful layout, impedance matching, and thermal management. You will work with a worldwide R&D team across time zones, own design from concept through validation, and collaborate with internal and external designers using Cadence APD or

Qualifications

• Requires a B.Eng in EE/EEE or similar with 5+ years in flip-chip-BGA design.
• Experience with high-speed SerDes and package-level SI/PI.
• Knowledge of Cadence APD preferred; equivalent tools considered.

Responsibilities

• Own ASIC flip-chip BGA package design, including impedance, crosstalk, and thermal aspects.
• Design high-frequency structures for SerDes, DDR and HBM as part of ASIC packages.
• Schedule and track multiple packages across time zones with internal/external teams.
• Collaborate with global teams including external vendors.

Skills

High-speed SerDes

Signal integrity

Power integrity

Cross-functional collaboration

Education

B.Eng (EE/EEE) or similar

M.Eng (EE/EEE) or similar (preferred)

Tools

Cadence APD

Allegro

Job description

Broadcom Inc. is seeking an experienced package design engineer to develop complex flip-chip-BGA packages for ASICs used in AI, networking, HPC, and 5G.

You will help enable high-performance SerDes at 200G and above, RF/microwave ADC/DAC, DDR, and HBM through careful layout, impedance matching, and thermal management. You will work with a worldwide R&D team across time zones, own design from concept through validation, and collaborate with internal and external designers using Cadence APD or