R&D Engineer Adv Tech Dev (PKE) / Sr. Staff

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; Singapore; On-site; SGD 120,000 - 190,000; Full time

Job summary

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED in Singapore seeks a senior IC packaging engineer to drive package selection and design for next‑gen silicon nodes, collaborating with IC design, system, and thermal teams.

You will ensure CPI/SI/PI and thermal requirements are met, lead packaging from concept through high‑volume production, and define assembly BOMs, processes, and troubleshooting for advanced technologies such as 2.5D, 3DIC and beyond.

Qualifications

• Educational degree in STEM fields required.
• Experience with advanced packaging and CPI concepts.
• Knowledge of 2.5D/3DIC, Si/Packaging integration.
• Familiarity with GD&T and mechanical drawings.
• Strong project management and leadership.
• Ability to collaborate with cross-functional teams.

Responsibilities

• Select optimum package solutions balancing cost, performance, manufacturability and reliability for new silicon nodes.
• Design custom packages with IC design, system design, and thermal teams.
• Ensure packages meet CPI/SI/PI and thermal requirements.
• Research, develop, and productize new materials such as TIM and underfill for 5nm/3nm.
• Manage packaging from concept to high volume production.
• Create BOMs, processes, and troubleshoot packaging issues.
• Collaborate with QA and customers to resolve quality issues.
• Interface with suppliers for new product bring-up and ramp.
• Support NPI bring-up, pkg qual, and sustain in production.

Skills

Advanced packaging

Signal integrity

Power integrity

Project leadership

Materials science

Thermal management

Vendor coordination

Quality engineering basics

Education

BS/MS/PhD in STEM/Materials/Electrical/Mechanical Engineering

Tools

Cadence APD

MCM packaging processes

Job description

Job Responsibilities

• Work with business unit marketing and IC design teams to select the optimum package solution on cost, performance, manufacturability, and reliability for new advanced silicon node products (5nm, 3nm, 2nm and beyond)
• Work with IC design, system design, package SI/PI & thermal engineering teams to design custom packages
• Ensure designed packages meet CPI, SI/PI, and stringent thermal requirements (1000sW+) of advanced node cutting edge silicon products
• Research, develop, and productize new materials such as TIM, build-up-film, underfill etc. in support advanced node silicon (5nm & 3/2nm) POR definition
• Manage IC packaging activity from concept through development, qualification and high volume production
• Be a specialist and able to define assembly BOM, process, troubleshoot, support on packaging issues on new advanced technology
• Implement, fine-tune, and productize newly developed technologies into HVM
• Create package design documentation and assembly instructions
• Work close with QA and customers to resolve quality issues
• Interface with packaging assembly and substrate suppliers for new product bring-up, qualification and production ramp
• Interface with other operations functional groups such as product engineering, foundry, test, and QA
• Participate in package technology development and/or other business productivity projects which have broad team impact (e.g. assembly process enhancement, new TIM material development etc.)
• Interface with tier #1 external customers for custom ASIC programs or as needed for development support, quality and/or other issue resolution
• Support NPI bring-up, pkg qual, and sustain support in production + multi-source activities for capacity, cost, & manufacturing flexibility needs

Job Requirements

• Education: BS/MS/PHD in STEM/Material Science/Electrical/Mechanical Engineering
• Experience: BS +8 years of experience or MS +6 years of experience or PhD + 3 years of experience is required
• Deep understanding of signal integrity and power integrity concepts such as characteristic impedance, s-parameters (RL, IL, FEXT/NEXT etc.), power plane impedance profile requirements and optimization etc.
• Strong authority on Cadence APD for custom substrate design
• Hands-on expertise of advanced and new assembly processes for flipchip, MCM packages, and 2.5D for advanced node silicon products (5nm, 3/2nm and beyond)
• Good understanding of materials as related to Chip Packaging Interaction (CPI)
• Familiarity with wafer BEOL as related to CPI (top metal, AP, passivation, UBM, bumping etc.)
• Knowledge of advanced substrate manufacturing/process is a must (e.g. SAP/mSAP, PSPI w/ Cu RDL etc.)
• In depth knowledge of failure analysis techniques on advanced node silicon (5nm, 3/2nm etc.) products with ELK and MiM structures
• Conceptual knowledge of package cost structure
• Strong project management, communication and leadership skills
• Must have knowledge of GD&T and be able to read/comprehend mechanical drawings
• Good understanding of manufacturing and quality engineering fundamentals (DOE, process capability indices, etc.)
• Job requirements are broad; the candidate must be able to expand and grow in multiple disciplines (manufacturing/quality, materials, electrical, thermal, and mechanical)
• Track record of innovation and subject matter expertise through journal publications and/or patent awards is desired
• Familiarity with advanced technologies such as 2.5D, 3DIC, glass substrate etc.