Principal DFT Engineer (Design-For-Test)

VOICE THE WAY PTE. LTD.; Singapore; On-site; SGD 80,000 - 110,000; Full time

Job summary

A technology company in Singapore is seeking an experienced individual to lead the architecture and implementation of Design-For-Test (DFT) features for SoC/IP. The ideal candidate will have over 10 years of experience in ASIC/SoC development and must possess a Master's degree in Computer Engineering or related fields. Strong proficiency in Verilog and DFT concepts is essential, alongside effective communication skills.

Qualifications

• Master’s degree or above in Computer Engineering, Electrical Engineering, or a related field.
• 10+ years of working experience in ASIC/SoC development.
• Strong communication and presentation skills in English.

Responsibilities

• Participate in the architecture and implementation of DFT features for SoC/IP.
• Perform CP and FT yield analysis based on diagnosis results.
• Develop and maintain in-house DFT flows and automation methods.

Skills

Design-For-Test (DFT) features

ASIC/SoC development

Verilog

DFT concepts and techniques

Synopsys Design Compiler

Tcl scripting

Communication skills

Education

Master’s degree in Computer Engineering or Electrical Engineering

Tools

Synopsys Design Compiler

DFT Compiler

TetraMAX

VCS

Mentor Tessent

Job description

Responsibilities

• Participate in the architecture and implementation of DFT (Design-For-Test) features for SoC/IP, including scan chain design, ATPG, pattern generation, simulation, and diagnosis;
• Perform CP (wafer-level) and FT (final test) yield analysis based on diagnosis results;
• Research and evaluate state-of-the-art DFT architectures and methodologies for SoC/IP designs;
• Develop and maintain in-house DFT flows and automation methods, and deploy them across multiple projects;
• Troubleshoot DFT-related issues during design implementation and silicon bring-up phases.

Qualifications and Skills

• Master’s degree or above in Computer Engineering, Electrical Engineering, or a related field;
• 10+ years of working experience in ASIC/SoC development;
• Solid understanding of Verilog and familiarity with front-end design flow;
• Knowledge of DFT concepts and techniques, including scan insertion, MBIST, and boundary scan;
• Proficient in using industry-standard tools such as Synopsys Design Compiler, DFT Compiler, TetraMAX, VCS, or Mentor Tessent;
• Experience with ATPG, MBIST, or diagnosis; experience in yield analysis is a strong plus;
• Skilled in scripting with Makefile, Tcl, Perl, or Python for design automation;
• Strong communication and presentation skills in English, with a passion for test methodologies and innovation.