Packaging Design Engineer, High-Speed SerDes & 2.5D/3DIC

Broadcom Inc.; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

Broadcom Inc. in Singapore seeks an experienced ASIC package design engineer to lead high‑speed SerDes flip‑chip‑BGA work for AI, networking, HPC and 5G applications. You will own impedance matching, signal/power integrity, manufacturability, reliability and thermal aspects in collaboration with a global team.

The candidate should have 5+ years in flip-chip-BGA package design (or 3+ with M.Eng), strong SI/PI knowledge, and Cadence APD experience is preferred; 2.5D/3DIC exposure is advantageous.

Qualifications

• B.Eng in EE/EEE or M.Eng with relevant years; flip-chip-BGA and high-speed SerDes experience required.
• Experience with package-level SI/PI to apply to package designs.
• Cadence APD (Allegro) experience preferred; other tools considered.

Responsibilities

• Overall design responsibility for ASIC package designs (layout/routing), including impedance matching, crosstalk, signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with experienced package engineering experts
• Package design of critical high frequency/datarate structures for SerDes, ADC/DAC, DDR, HBM, etc.
• Schedule, prioritize, and track work across multiple projects simultaneously
• General flip-chip BGA package design and engineering
• Cooperate with worldwide team (multiple time zones), including co-design with internal team members and external (Vendor) designers

Skills

High-speed SerDes

Signal integrity

Power integrity

Project management

Education

B.Eng (EE/EEE) or equivalent

M.Eng (EE/EEE) or equivalent

Tools

Cadence APD (Allegro Package Designer)

2.5D/3DIC design tools

Job description

Broadcom Inc. in Singapore seeks an experienced ASIC package design engineer to lead high‑speed SerDes flip‑chip‑BGA work for AI, networking, HPC and 5G applications. You will own impedance matching, signal/power integrity, manufacturability, reliability and thermal aspects in collaboration with a global team.

The candidate should have 5+ years in flip-chip-BGA package design (or 3+ with M.Eng), strong SI/PI knowledge, and Cadence APD experience is preferred; 2.5D/3DIC exposure is advantageous.