Design Verification Engineer | IP/SOC & Low-Power

MediaTek; Singapore; On-site; SGD 80,000 - 110,000; Full time

Job summary

MediaTek in Singapore is hiring a verification engineer to develop and verify Module/IP/SOC designs using UVM, SystemVerilog, Verilog and SystemC. You will implement test plans, build verification environments and reference models, and perform randomization-based coverage driven verification.

The role also covers low power and formal verification, with hands-on debugging and verification automation, ensuring closure of functional and code coverage.

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering or related field.
• Strong coding skills in C/C++, Perl, Python, and Unix/Linux shell.
• Experience with UVM/SystemVerilog/Verilog/SystemC verification environments.

Responsibilities

• Module/IP/SOC design verification.
• Develop and review test plans.
• Develop verification environment/testbench at Module/IP/SOC level.
• Develop verification IP and reference model.
• Implement test with randomization-based coverage driven verification methodology.
• Implement functional and functional/code coverage closure.
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC.
• Low Power verification.
• Formal verification.
• Verification automation flow.

Skills

C/C++

Perl

Python

Unix/Linux shell

UVM

SystemVerilog

Verilog

SystemC

Low Power verification

Formal verification

Education

Bachelor’s degree in Electrical/Computer Engineering

Tools

EDA tools

Job description

MediaTek in Singapore is hiring a verification engineer to develop and verify Module/IP/SOC designs using UVM, SystemVerilog, Verilog and SystemC. You will implement test plans, build verification environments and reference models, and perform randomization-based coverage driven verification.

The role also covers low power and formal verification, with hands-on debugging and verification automation, ensuring closure of functional and code coverage.