Senior SoC Verification Engineer — SystemVerilog & UVM Expert

Realtek Singapore Private Limited; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

Realtek Singapore Private Limited is seeking an experienced ASIC/SoC verification engineer to join our high‑speed digital design team. You will develop test plans, verification environments, and directed tests to ensure functional compliance of complex IPs.

You will collaborate with digital design teams, debug testcases, and deliver robust designs in a fast moving environment requiring strong communication and documentation skills.

Qualifications

• 6+ years of SOC/IP verification experience required.
• Strong verbal and written communication and documentation skills.
• Experience with SystemVerilog/UVM and Python is preferred.

Responsibilities

• Develop detailed module and SoC level test plans based on design specs.
• Develop ASIC verification environments including stimulus, checkers, assertions, monitors and scoreboards.
• Develop directed and constrained-random verification tests and simulate using EDA tools to verify functional spec.
• Execute verification plans, including design bring-up, DV bring-up, regression enabling for all features.
• Collaborate with digital design team to debug functional test cases and deliver functionally correct designs.
• Demonstrate ability to deliver results in a fast-moving, dynamic environment.

Skills

SOC/IP verification

SystemVerilog/UVM

Python

OO language

Education

Bachelor/Master in Electronics/Electrical Engineering

Job description

Realtek Singapore Private Limited is seeking an experienced ASIC/SoC verification engineer to join our high‑speed digital design team. You will develop test plans, verification environments, and directed tests to ensure functional compliance of complex IPs.

You will collaborate with digital design teams, debug testcases, and deliver robust designs in a fast moving environment requiring strong communication and documentation skills.