Senior IC Verification Engineer (UVM/SystemVerilog)

Ethos Search Associates Pte Ltd; Singapore; On-site; SGD 50,000 - 70,000; Full time

Job summary

Ethos Search Associates Pte Ltd is seeking a verification engineer in Singapore. The role involves developing test plans and environments for IC design and requires a Bachelor's or Master's degree in Electrical or Electronics Engineering along with hands-on experience in Silicon/IP verification using SystemVerilog and UVM. Candidates should possess strong communication and analytical skills, along with familiarity with leading EDA software tools like Cadence and Synopsys.

Qualifications

• 1 year or more experience in Silicon/IP verification.
• Hands-on experience using SystemVerilog/UVM.
• Strong understanding of verification processes.

Responsibilities

• Develop and Review Test Plan based on IC design specification.
• Develop constrained-Random verification environment for complex DUT.
• Implement coverage matrix using cover point and assertion.

Skills

Silicon/IP verification

SystemVerilog

UVM

Communication skills

Analytical skills

Education

Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering

Tools

Cadence

Synopsys

Job description

Ethos Search Associates Pte Ltd is seeking a verification engineer in Singapore. The role involves developing test plans and environments for IC design and requires a Bachelor's or Master's degree in Electrical or Electronics Engineering along with hands-on experience in Silicon/IP verification using SystemVerilog and UVM. Candidates should possess strong communication and analytical skills, along with familiarity with leading EDA software tools like Cadence and Synopsys.