[2027 Campus Hire] Design Verification Engineer

MediaTek; Singapore; On-site; SGD 80,000 - 110,000; Full time

Job summary

MediaTek in Singapore is hiring a verification engineer to develop and verify Module/IP/SOC designs using UVM, SystemVerilog, Verilog and SystemC. You will implement test plans, build verification environments and reference models, and perform randomization-based coverage driven verification.

The role also covers low power and formal verification, with hands-on debugging and verification automation, ensuring closure of functional and code coverage.

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering or related field.
• Strong coding skills in C/C++, Perl, Python, and Unix/Linux shell.
• Experience with UVM/SystemVerilog/Verilog/SystemC verification environments.

Responsibilities

• Module/IP/SOC design verification.
• Develop and review test plans.
• Develop verification environment/testbench at Module/IP/SOC level.
• Develop verification IP and reference model.
• Implement test with randomization-based coverage driven verification methodology.
• Implement functional and functional/code coverage closure.
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC.
• Low Power verification.
• Formal verification.
• Verification automation flow.

Skills

C/C++

Perl

Python

Unix/Linux shell

UVM

SystemVerilog

Verilog

SystemC

Low Power verification

Formal verification

Education

Bachelor’s degree in Electrical/Computer Engineering

Tools

EDA tools

Job description

• Develop verification IP and reference model.
• Implement test with randomization-based coverage driven verification methodology.
• Implement functional and functional/code coverage closure.
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC.
• Low Power verification.
• Formal verification.

Job Description

[What you will do]

• Module/IP/SOC design verification.
• Develop and review test plans.
• Develop verification environment/testbench in Module/IP/SOC level.
• Develop verification IP and reference model.
• Implement test with randomization-based coverage driven verification methodology.
• Implement functional and functional/code coverage closure.
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC.
• Low Power verification.
• Formal verification.
• Verification automation flow.

Main Requirements and Qualifications

[What you will bring]

• - Bachelor’s degree in Electrical Engineering, Computer Engineering or related
• - Dedication to continuous self-developing and learning new technologies
• - Good knowledge of chip design flow and EDA tools
• - Strong coding skills in C/C++, Perl, Python, and Unix/Linux shell
• Location: One North, Singapore

[About the team]

ASIC DV Team focus on developing full and advanced verification methodology IP/SOC. You will have chance to work on challenging projects that attractive and be immersed in leading tech e.g.: WiFi, 5G, AR/VR, AI, Cloud Networking. A comprehensive program for professional development / career growth will be provided to the new joiner and he/she will have chance to learn from the best expert in this area.

[Why MediaTek?]

MediaTek Incorporated (TWSE: 2454) is the world’s 5th largest global fabless semiconductor company. Joining MediaTek means becoming part of a team that powers over 2 billion ICs worldwide, enriching and enhancing everyday life. Our chipsets are integral to a wide range of products, from smartphones, mobile devices to home and IoT devices, in entertainment and multimedia products, and provide connectivity and communication solutions that keep people connected with friends and their families with access to online resources. Working at MediaTek offers you the opportunity to contribute to the world through the devices we use in our daily lives – it’s more than just a job, it’s a chance to make a meaningful impact. – Join us now!