Design Verification-Staff

Uni Connect; Singapore; On-site; SGD 90,000 - 150,000; Full time

Job summary

Uni Connect in Singapore is seeking a hands-on ASIC/SoC verification engineer to verify digital and mixed-signal designs, including multi-core CPUs, DSPs, security hardware for IoT applications.

The role emphasizes building test plans, developing UVM-based test benches, writing C-based tests, and ensuring high coverage with automated debugging and root-cause analysis.

Qualifications

• 5–8 years experience in block, sub-system, and full-chip verification.
• Delivered multiple chips functioning to specification.
• Identify and manage verification deliverables, milestones, and schedules.
• Proactively identify potential verification risks and develop mitigation strategies.
• Collaborate with design, architecture, and software teams to verify design intent.

Responsibilities

• Verify digital and mixed-signal SoC designs with multiple CPUs, DSPs, and security hardware.
• Develop test plans at block, sub-system, and chip level.
• Execute SoC-based verification at full-chip level.
• Architect and implement scalable test benches using SystemVerilog and UVM.
• Develop test cases, stimulus, and checkers to achieve high coverage.
• Automate the test environment for randomized testing and scoreboarding.

Skills

SystemVerilog (UVM)

Verilog

C/C++

Python

Perl

Makefile

Education

BSEE /MSEE

Job description

Singapore, Singapore | Posted on 12/16/2024

You will be responsible for verifying digital and mixed-signal designs, including systems-on-chip with multiple CPUs, digital signal processors, security hardware, and other logic for IoT applications.

Specific responsibilities include:

• The right candidate will be a self-starter who assumes full ownership of DV tasks and delivers high-quality results.
  
• Develop test plans at block, sub-system, and chip level.
  
• Execute SoC-based verification at full-chip.
  
• Write C-based lib packages and tests.
  
• Architect and implement scalable and reusable test benches using SystemVerilog and UVM.
  
• Develop comprehensive test cases, stimulus generation, and checkers to achieve high coverage.
  
• Automating the test environment for randomized testing and scoreboarding.
  
• Utilize advanced debugging techniques to identify and resolve design and verification issues.
  
• Perform root-cause analysis and work with design teams to fix identified issues
  
• Define and track functional and code coverage metrics to ensure thorough verification.
  
• Ensure that verification quality meets or exceeds industry standards and project requirements.
  
• Edge-based AI inference is preferred.
  

Requirements

• BSEE /MSEE 5-8 years Degree of experience in block, sub-system, and full-chip verification
  
• Should have delivered multiple chips functioning to Specification.
  
• Identify and manage verification deliverables, milestones, and schedules.
  
• Proactively identify potential verification risks and develop mitigation strategies.
  
• Collaborate with design, architecture, and software teams to understand and verify design intent.
  
• Communicate verification progress, issues, and results to stakeholders and management.
  
• Strong in understanding multiple architectures, integrating 3rd party IPs/VIPs, and working with mixed-signal designs with low-power design and verification challenges
  
• Strong understanding/exposure to Design Verification for low-power battery-operated designs is highly desired.
  
• C-based verification in an SoC environment is required
  
• Experience with ARM processor-based designs and low-power design techniques is a plus.
  
• Languages: SystemVerilog (UVM), Verilog, C/C++, Python, Perl or Makefile
  
• Technologies: ARM M/RISC-V (Preferred), AMBA AXI/AHB/APS, DMA, Flow Control, Serial Devices, Qo5
  
• Preferred technologies: MIPI(CSI/DSI), Crypto, OTP, DSP, Low-Power