Senior Verification Engineer: UVM & SystemVerilog Expert

UST; Singapore; On-site; SGD 70,000 - 120,000; Full time

Job summary

UST in Singapore is seeking a verification engineer to apply UVM, SystemVerilog, Verilog and SVA in challenging tasks. You will develop and implement state-of-the-art verification methodologies including co-simulation, system emulation, and mixed-mode simulation.

The role requires a Masters or Bachelors in Electrical or Computer Engineering and at least 3 years of relevant experience; proficient in Ethernet and familiar with SPI, UART, and I2C protocols; collaborate effectively to deliver

Qualifications

• Masters or Bachelors in Electrical or Computer Engineering.
• Minimum 3 years of relevant verification experience.
• Proficient in UVM, SystemVerilog, Verilog, Ethernet; familiarity with SPI/UART/I2C preferred.

Responsibilities

• Apply UVM, SystemVerilog, Verilog and SVA in verification tasks.
• Develop and implement verification methodologies including co-simulation and emulation.
• Collaborate within a team to deliver high-quality verification deliverables.

Skills

UVM

SystemVerilog

Verilog

Ethernet

C/C++

Education

Bachelor's or Master's in Electrical Engineering or Computer Engineering

Tools

Palladium Z1

HAPS

Zebu platforms

co-simulation

system emulation

mixed-mode simulation/emulation

Job description

UST in Singapore is seeking a verification engineer to apply UVM, SystemVerilog, Verilog and SVA in challenging tasks. You will develop and implement state-of-the-art verification methodologies including co-simulation, system emulation, and mixed-mode simulation.

The role requires a Masters or Bachelors in Electrical or Computer Engineering and at least 3 years of relevant experience; proficient in Ethernet and familiar with SPI, UART, and I2C protocols; collaborate effectively to deliver