Design Verification Engineer

BITSILICA PTE. LTD.; Singapore; On-site; SGD 78,000 - 112,000; Full time

Job summary

BITSILICA PTE. LTD. in Singapore is seeking a Design Verification Engineer with 4+ years of experience to verify FPGA/ASIC SoCs using SystemVerilog and UVM. The role emphasizes IP verification, low power UPF based verification, and a strong scripting ability.

Candidates should be proficient in Verilog, SystemVerilog, C, C++, and familiar with Cadence IUS, Synopsys VCS, and Verdi. This is a hands-on position requiring attention to detail and collaboration with hardware teams.

Skills

FPGA SoC verification

ASIC SoC verification

SystemVerilog & UVM

Automation skills

IP verification

Low-power UPF verification

Tools

Cadence IUS

Synopsys VCS

Verdi

Job description

Design Verification Engineer

Experience : 4+ Years

Salary Range :SGD 7000-10000

Skills Required:

• FPGA SoC Verification Skills
• ASIC SoC Verification Skills
• System Verilog and UVM Skills
• Automation Skills .
• IP Verification Skills
• Low power UPF based verification skills

Technical Expertise

Languages :Verilog, System Verilog, C, C++.

Verification Methodologies:UVM, OVM.

Scripting Languages:Perl,C-shell.

Simulators:Cadence IUS, Synopsys VCS, Verdi.

Protocols:PCIe,AGPT,CFDM,SPI,ISO7816,DDR3, LPDDR2, GPIO, AXI, AHB, APB, JTAG, WDT, GPT.