Lead engineer-Design verification

Uni Connect; Singapore; On-site; SGD 80,000 - 120,000; Full time

Job summary

A leading technology firm in Singapore is seeking a skilled design verification engineer to be responsible for verifying digital and mixed-signal designs. The ideal candidate should have a BSEE/MSEE with 8-12 years of experience in verification, proficiency in SystemVerilog and C/C++, and a strong understanding of low-power battery-operated designs. Key responsibilities include developing test plans, automating test environments, and collaborating with design teams to resolve issues. This position offers opportunities for advanced project involvement in an innovative environment.

Qualifications

• 8-12 years of experience in block, sub-system, and full-chip verification.
• Experience with ARM processor-based designs and low-power techniques is a plus.
• C-based verification in an SoC environment is required.

Responsibilities

• Assume full ownership of DV tasks and deliver high-quality results.
• Develop test plans at block, sub-system, and chip level.
• Automate the test environment for randomized testing.

Skills

Self-starter

Strong understanding of multiple architectures

Proficient in SystemVerilog (UVM)

C/C++ programming

Advanced debugging techniques

Education

BSEE / MSEE

Tools

SystemVerilog

Verilog

C/C++

Python

Job description

singapore, Singapore | Posted on 12/02/2024

You will be responsible for verifying digital and mixed-signal designs, including systems-on-chip with multiple CPUs, digital signal processors, security hardware, and other logic for IoT applications.

Specific responsibilities include:

• The right candidate will be a self-starter who assumes full ownership of DV tasks and delivers high-quality results.
  
• Develop test plans at block, sub-system, and chip level.
  
• Execute SoC-based verification at full-chip.
  
• Write C-based lib packages and tests.
  
• Architect and implement scalable and reusable test benches using SystemVerilog and UVM.
  
• Develop comprehensive test cases, stimulus generation, and checkers to achieve high coverage.
  
• Automating the test environment for randomized testing and scoreboarding.
  
• Utilize advanced debugging techniques to identify and resolve design and verification issues.
  
• Perform root-cause analysis and work with design teams to fix identified issues
  
• Define and track functional and code coverage metrics to ensure thorough verification.
  
• Ensure that verification quality meets or exceeds industry standards and project requirements.
  
• Edge-based AI inference is preferred.
  

Requirements

Requirements

Requirements

What you need to have to be successful

• BSEE /MSEE 8-12 years Degree of experience in block, sub-system, and full-chip verification
  
• Should have delivered multiple chips functioning to Specification.
  
• Identify and manage verification deliverables, milestones, and schedules.
  
• Proactively identify potential verification risks and develop mitigation strategies.
  
• Collaborate with design, architecture, and software teams to understand and verify design intent.
  
• Communicate verification progress, issues, and results to stakeholders and management.
  
• Strong in understanding multiple architectures, integrating 3rd party IPs/VIPs, and working with mixed-signal designs with low-power design and verification challenges
  
• Strong understanding/exposure to Design Verification for low-power battery-operated designs is highly desired.
  
• C-based verification in an SoC environment is required
  
• Experience with ARM processor-based designs and low-power design techniques is a plus.
  
• Languages: SystemVerilog (UVM), Verilog, C/C++, Python, Perl or Makefile
  
• Technologies: ARM M/RISC-V (Preferred), AMBA AXI/AHB/APS, DMA, Flow Control, Serial Devices, Qo5
  
• Preferred technologies: MIPI(CSI/DSI), Crypto, OTP, DSP, Low-Power