A research scientist working on Chip-to-Wafer (C2W) bonding processes primarily focuses on the development, optimization, characterization, and integration of advanced bonding techniques for semiconductor packaging and heterogeneous integration applications.
Job Description
Process Development and Optimization
- Innovate and develop new C2W bonding capabilities, including hybrid, fusion, thermocompression, and eutectic bonding methods.
- Investigate and refine related processes like wafer cleaning, planarization (CMP), and post-bonding annealing, addressing critical factors such as warpage, bonding strength, and alignment accuracy.
Evaluation and Characterization
- Plan and execute comprehensive evaluations of processes, materials, and equipment.
- Conduct experiments for process characterization, data collection, and analysis to drive quality improvements.
- Assess the thermal, mechanical, and electrical performance of the bonded structures, ensuring they meet the requirements for advanced applications like AI accelerators and 3D-ICs.
Project Collaboration and Integration
- Work closely with process integration teams, project leaders, and senior staff to align on project requirements and troubleshoot issues for industry and grant projects.
- Collaborate with internal and external stakeholders, including industry partners and equipment suppliers, to define technology roadmaps and develop next-generation capabilities.
Documentation and Intellectual Property
- Generate detailed engineering reports, research papers, and technical documents.
- Contribute to the creation of new intellectual properties (IPs), file patents, and document know-how related to heterogeneous integration platforms.
- Publish research findings in prestigious scientific journals and present at conferences.
Mentorship and Expertise
- Act as a subject matter expert (SME) for both internal and external stakeholders.
- Mentor and inspire scientists, engineers and talents in the field of advanced semiconductor packaging technology.
Job Requirements
- PhD in Materials Science, Mechanical Engineering, Physics, Chemistry, Electronics, or Electrical Engineering.
- Experience in chip to wafer bonding process development or packaging R&D, with a strong track record in advanced packaging technologies is added advantage.
- Relevant experience in semiconductor packaging or process development.