Senior RTL Engineer: SoC Design, Tape-Out & Impact

Capgemini Engineering; Almada; On-site; EUR 65,000 - 90,000; Full time

Benefits offered by this job

Health and life insurance

Referral program with bonuses

Training & certifications

International projects

Great office locations

Job summary

Capgemini Engineering in Caparica, Portugal, seeks a Senior RTL Engineer to drive digital design from architecture through tape-out. You will deliver high‑performance, power‑efficient products and collaborate across Verification, Synthesis, STA, and Physical Design teams.

The role requires hands-on RTL with Verilog/SystemVerilog or VHDL, plus experience in microarchitecture development, SoC integration, and CPU familiarity. Strong problem solving and teamwork are essential.

Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering or related field.
• 6+ years of experience in RTL/ASIC/SoC/VLSI design.
• Strong knowledge of Verilog, SystemVerilog, and/or VHDL.

Responsibilities

• Drive RTL design activities from architecture to tape-out.
• Develop microarchitectures for complex digital blocks and SoCs.
• Implement RTL designs using Verilog, SystemVerilog, or VHDL.
• Execute RTL quality checks (Lint, CDC, Low Power).
• Develop timing constraints and support synthesis and timing closure.
• Collaborate with Verification, Synthesis, STA, Physical Design, and DFT teams.
• Create and maintain automation scripts and design flows.

Skills

RTL design

SoC development

SystemVerilog

VHDL

ASIC/VLSI

Python

Perl

C

CPU architectures

Education

Bachelor's or Master's in Electrical Engineering

Tools

Verilog

SystemVerilog

VHDL

Lint

CDC

STA

Synthesis Tools

Job description

Capgemini Engineering in Caparica, Portugal, seeks a Senior RTL Engineer to drive digital design from architecture through tape-out. You will deliver high‑performance, power‑efficient products and collaborate across Verification, Synthesis, STA, and Physical Design teams.

The role requires hands-on RTL with Verilog/SystemVerilog or VHDL, plus experience in microarchitecture development, SoC integration, and CPU familiarity. Strong problem solving and teamwork are essential.