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Capgemini Engineering is seeking a Senior RTL Engineer to drive digital design from architecture to tape-out for high-performance, power-efficient SoCs. You will define microarchitectures, implement RTL in Verilog/SystemVerilog/VHDL, and collaborate across verification, synthesis, and physical design teams to ensure timing, power and area targets.
The role requires 6+ years in RTL/ASIC/VLSI, strong HDL skills, and experience with Lint/CDC/Low Power methodologies, STA, and CPU architectures.
At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.
As a Senior RTL Engineer, you will be responsible for driving digital design activities from architecture definition through tape-out, ensuring the successful delivery of high-performance and power-efficient products.
In this role, you will
Capgemini is an AI-powered global business and technology transformation partner, delivering tangible business value. We imagine the future of organizations and make it real with AI, technology and people. With our strong heritage of nearly 60 years, we are a responsible and diverse group of 420,000 team members in more than 50 countries. We deliver end-to-end services and solutions with our deep industry expertise and strong partner ecosystem, leveraging our capabilities across strategy, technology, design, engineering and business operations.