Analog IC DV Engineer – SoC Verification

Capgemini Engineering; Porto; Hybrid; EUR 45,000 - 65,000; Full time

Benefits offered by this job

Hybrid work

Health and life insurance

Referral program with bonuses

Great office locations

International projects

Job summary

Capgemini Engineering in Porto seeks Design Verification Engineers to join our Semiconductor team and contribute to verification of complex digital IPs and SoCs on advanced semiconductor projects.

You will own verification in prototype and SoC environments, establish benchmarks, and lead DV methodology across platforms. Strong SystemVerilog, UVM/OVM, and UVC component experience are required. Hybrid work and international collaboration are key benefits.

Qualifications

• Degree in Electrical Engineering, Electronics, Computer Engineering, Microelectronics or a related field.
• +4 years of experience.
• Strong SystemVerilog knowledge with UVM/OVM experience.
• Experience creating UVC components or sequences is required.
• Knowledge of two or more protocols (AHB/AXI, PCIe/CXL, USB, DDR, Serial); expertise in one protocol for senior roles.
• Proficient in Perl/TCL/Python scripting.
• English fluency.

Responsibilities

• Own verification of IPs and SoCs in prototype and SoC design environments.
• Establish functional and performance benchmarks.
• Lead the definition, execution and continuous improvement of DV methodology and tools flow across verification platforms.
• DV from RTL to emulation to deliver fully functional IPs/SoCs.

Skills

SystemVerilog

UVM/OVM

Constrained Random

UVC components

Perl scripting

Python scripting

TCL scripting

English fluent

Education

Electrical/Electronics/Computer Engineering degree

Tools

UVC components

EDA tools

Perl

TCL

Job description

Capgemini Engineering in Porto seeks Design Verification Engineers to join our Semiconductor team and contribute to verification of complex digital IPs and SoCs on advanced semiconductor projects.

You will own verification in prototype and SoC environments, establish benchmarks, and lead DV methodology across platforms. Strong SystemVerilog, UVM/OVM, and UVC component experience are required. Hybrid work and international collaboration are key benefits.