Analog IC Engineer - Semiconductors 1

Capgemini Engineering; Fundão; Hybrid; EUR 45,000 - 60,000; Full time

Benefits offered by this job

Hybrid work

Health and life insurance

Referral bonuses

Great office locations

Job summary

Capgemini Engineering is seeking Design Verification Engineers to join its Semiconductor team in Portugal. You will verify complex digital IPs and SoCs across advanced projects, from RTL to emulation, helping build robust DV processes and standards.

The role requires a degree in electrical/electronics/computer engineering with 4+ years experience, strong SystemVerilog and UVM/OVM, UVC experience, scripting skills, and a proactive, international mindset with fluent English.

Qualifications

• Degree in Electrical Engineering, Electronics, Computer Engineering, Microelectronics or a related field.
• +4y of experience.
• Sound knowledge of SystemVerilog, and good experience in Constrained Random and Coverage Driven Verification with UVM/OVM.
• Experience in creating any UVC components or sequences is a must.
• Basic knowledge on at least two of these: AHB/AXI, PCIe/CXL, USB, DDR, Serial protocols, Processor Verification etc.
• Should be comfortable in updating the existing verification environment for feature updates. (Bring-up/Architect UVM based Test bench from Scratch is a strong plus) EDA simulation/debugging tools agnostic.
• Good knowledge of Perl/TCL/Python scripting.
• Domain expertise on any one of these for senior and above: CPU processor/server, multimedia, automotive, Ethernet, Mobile.
• Strong analytical and debugging skills, with the ability to collaborate effectively within multidisciplinary and international engineering teams.
• Fluent in English.

Responsibilities

• Own verification of IP’s and SoC’s in prototype and SoC design environment;
• Establish functional and performance benchmarks;
• Lead the definition, execution, and continuous improvement of a robust design verification (DV) methodology and tools flow across different verification platforms;
• IP and SoC design verification (DV), from the RTL level to emulation, resulting in fully functional and performant IP’s/SoC’s.

Skills

SystemVerilog

UVM/OVM

UVC development

Perl scripting

Python scripting

English fluency

AXI/PCIe knowledge

Education

Electrical/ Electronics/ Computer Engineering degree

Tools

UVC tools

Job description

CAPGEMINI ENGINEERING

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life‑saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.

YOUR ROLE

We are looking for Design Verification Engineers to join our Semiconductor team and contribute to the verification of complex digital IPs and SoCs across advanced semiconductor projects.

Your Responsibilities May Include

• Own verification of IP’s and SoC’s in prototype and SoC design environment;
• Establish functional and performance benchmarks;
• Lead the definition, execution, and continuous improvement of a robust design verification (DV) methodology and tools flow across different verification platforms;
• IP and SoC design verification (DV), from the RTL level to emulation, resulting in fully functional and performant IP’s/SoC’s.

YOUR PROFILE

• Degree in Electrical Engineering, Electronics, Computer Engineering, Microelectronics or a related field.
• + 4y of experience.
• Sound knowledge of SystemVerilog, and good experience in Constrained Random and Coverage Driven Verification with UVM/OVM.
• Experience in creating any UVC components or sequences is a must.
• Basic knowledge on at least two of these: AHB/AXI, PCIe/CXL, USB, DDR, Serial protocols, Processor Verification etc. Expertise in one protocol is a must for Senior and above.
• Should be comfortable in updating the existing verification environment for feature updates. (Bring-up/Architect UVM based Test bench from Scratch is a strong plus) EDA simulation/debugging tools agnostic.
• Good knowledge of Perl/TCL/Python scripting.
• Domain expertise on any one of these for senior and above: CPU processor/server, multimedia, automotive, Ethernet, Mobile.
• Strong analytical and debugging skills, with the ability to collaborate effectively within multidisciplinary and international engineering teams.
• Fluent in English.

What You’ll Love About Working Here

• Join a multicultural and inclusive team environment.
• Enjoy a supportive atmosphere promoting work life balance.
• Hybrid work.
• Your career growth is central to our mission. Our array of career growth programs and diverse professionals are crafted to support you in exploring a world of opportunities.
• Access valuable training and certifications in cutting edge technologies.
• Engage in exciting national and international projects.
• Health and life insurance.
• Referral program with bonuses for talent recommendations.
• Great office locations.

About Capgemini

Capgemini is the business transformation partner for enterprises in the age of AI. We help organizations imagine and build an intelligent, sustainable future, combining AI, technology and human ingenuity to transform how they operate, innovate and grow. With unique end‑to‑end capabilities spanning strategy, technology, engineering and intelligent operations, we bring together deep industry expertise and market‑leading capabilities in AI, cloud and data to turn ambition into measurable business outcomes at scale. Supported by a robust ecosystem of partners and nearly 60 years of expertise, Capgemini is a responsible and diverse global organization of over 410,000 team members in more than 50 countries.