Senior STA Engineer - ASIC Timing & Low Power

Intellectual Capital Resources Ltd; Noord-Brabant; On-site; EUR 60,000 - 90,000; Full time

Job summary

Intellectual Capital Resources Ltd in the Netherlands is seeking an experienced STA Engineer to drive timing, power and implementation readiness for next-generation ASIC designs. You will join a highly technical engineering team and contribute across timing, low power and implementation readiness, with strong opportunities for career progression.

The role involves developing and maintaining SDC timing constraints, supporting static timing analysis, working with UPF and low power methodologies,

Qualifications

• Experience in ASIC implementation/STA or closely related discipline.
• Strong knowledge of SDC and static timing analysis.
• Experience with synthesis and front-end implementation flows.
• Understanding of UPF and low power design.
• Experience with SRAMs, memory macros and third-party IP.
• Good understanding of physical design and floorplanning.
• Previous tapeout experience is advantageous.
• Experience working in a Linux environment.

Responsibilities

• Developing and maintaining SDC timing constraints across internal designs and third-party IP.
• Supporting static timing analysis and timing closure.
• Working with UPF and low power methodologies across different design partitions.
• Preparing synthesis and implementation collateral.
• Working closely with physical design teams and external implementation partners.
• Contributing to floorplanning, partitioning and implementation planning.
• Supporting power analysis, DFT and wider implementation activities.

Skills

SDC timing

Static timing analysis

UPF

Low power design

Synthesis flows

Tapeout experience

Linux environment

Job description

Intellectual Capital Resources Ltd in the Netherlands is seeking an experienced STA Engineer to drive timing, power and implementation readiness for next-generation ASIC designs. You will join a highly technical engineering team and contribute across timing, low power and implementation readiness, with strong opportunities for career progression.

The role involves developing and maintaining SDC timing constraints, supporting static timing analysis, working with UPF and low power methodologies,