STA Engineer

IC Resources; Eindhoven; On-site; EUR 65,000 - 90,000; Full time

Job summary

IC Resources is seeking an STA Engineer to join a leading semiconductor firm developing next-generation ASIC technology. The role focuses on preparing designs for physical implementation, with emphasis on timing, power, and implementation readiness within a growing engineering team.

The ideal candidate will contribute to timing constraints, SDC/UPF methodologies, synthesis, and floorplanning while collaborating with internal design teams and external partners to drive successful tapeouts and

Qualifications

• Experience in ASIC implementation and static timing analysis.
• Strong knowledge of SDC and timing closure.
• Experience with synthesis and front-end implementation flows.
• Practical understanding of UPF and low power design.
• Experience with SRAMs, memory macros and third-party IP.
• Good understanding of physical design and floorplanning.
• Tapeout experience would be advantageous.
• Experience working in a Linux environment.

Responsibilities

• Developing and maintaining SDC timing constraints across internal designs and third-party IP.
• Supporting static timing analysis and timing closure.
• Working with UPF and low power methodologies across different design partitions.
• Preparing synthesis and implementation collateral.
• Working closely with physical design teams and external implementation partners.
• Contributing to floorplanning, partitioning and implementation planning.
• Supporting power analysis, DFT and wider implementation activities.

Skills

Static timing analysis

ASIC implementation

Front-end implementation flows

UPF and low power design

Floorplanning

Tapeout experience

Linux

Tools

Linux environment

Job description

All candidates must have the right to work in the Netherlands

An exciting opportunity has arisen for an STA Engineer to join an innovative semiconductor company developing next-generation ASIC technology.

Working within a growing and highly technical engineering team, the STA Engineer will play an important role in preparing complex designs for physical implementation, with responsibility across timing, low power and implementation readiness. With the company continuing to grow, the role offers excellent opportunities for career progression and the potential to develop into a technical leadership position over time.

The role will involve:

• Developing and maintaining SDC timing constraints across internal designs and third-party IP
• Supporting static timing analysis and timing closure
• Working with UPF and low power methodologies across different design partitions
• Preparing synthesis and implementation collateral
• Working closely with physical design teams and external implementation partners
• Contributing to floorplanning, partitioning and implementation planning
• Supporting power analysis, DFT and wider implementation activities

The ideal candidate will have:

• Experience in ASIC implementation, STA or a closely related discipline
• Strong knowledge of SDC and static timing analysis
• Experience with synthesis and front-end implementation flows
• Practical understanding of UPF and low power design
• Experience working with SRAMs, memory macros and third-party IP
• Good understanding of physical design and floorplanning
• Previous tapeout experience would be advantageous
• Experience working in a Linux environment