STA Engineer — ASIC Timing & Power

IC Resources; Eindhoven; On-site; EUR 65,000 - 90,000; Full time

Job summary

IC Resources is seeking an STA Engineer to join a leading semiconductor firm developing next-generation ASIC technology. The role focuses on preparing designs for physical implementation, with emphasis on timing, power, and implementation readiness within a growing engineering team.

The ideal candidate will contribute to timing constraints, SDC/UPF methodologies, synthesis, and floorplanning while collaborating with internal design teams and external partners to drive successful tapeouts and

Qualifications

• Experience in ASIC implementation and static timing analysis.
• Strong knowledge of SDC and timing closure.
• Experience with synthesis and front-end implementation flows.
• Practical understanding of UPF and low power design.
• Experience with SRAMs, memory macros and third-party IP.
• Good understanding of physical design and floorplanning.
• Tapeout experience would be advantageous.
• Experience working in a Linux environment.

Responsibilities

• Developing and maintaining SDC timing constraints across internal designs and third-party IP.
• Supporting static timing analysis and timing closure.
• Working with UPF and low power methodologies across different design partitions.
• Preparing synthesis and implementation collateral.
• Working closely with physical design teams and external implementation partners.
• Contributing to floorplanning, partitioning and implementation planning.
• Supporting power analysis, DFT and wider implementation activities.

Skills

Static timing analysis

ASIC implementation

Front-end implementation flows

UPF and low power design

Floorplanning

Tapeout experience

Linux

Tools

Linux environment

Job description

IC Resources is seeking an STA Engineer to join a leading semiconductor firm developing next-generation ASIC technology. The role focuses on preparing designs for physical implementation, with emphasis on timing, power, and implementation readiness within a growing engineering team.

The ideal candidate will contribute to timing constraints, SDC/UPF methodologies, synthesis, and floorplanning while collaborating with internal design teams and external partners to drive successful tapeouts and