STA Engineer

IC Resources; Noord-Brabant; Vor Ort; EUR 55.000 - 85.000; Vollzeit

Zusammenfassung

IC Resources in the Netherlands seeks an STA Engineer to advance next-generation ASIC timing and power-aware design, coordinating with verification and physical design teams. You will develop constraints and support STA, UPF, and low-power methodologies across partitions, while preparing synthesis and implementation collateral.

The ideal candidate will have experience with ASIC implementation, memory macros, third-party IP, and Linux.

Qualifikationen

• Experience in ASIC timing and STA integration.
• Strong knowledge of SDC and static timing analysis.
• Experience with synthesis and front-end implementation flows.
• Understanding UPF and low power design.
• Experience with memory macros and third-party IP.
• Familiarity with Linux environment.
• Tapeout experience is advantageous.

Aufgaben

• Develop and maintain SDC timing constraints across internal designs and third-party IP.
• Support static timing analysis and timing closure; work with UPF and low power methodologies across partitions.
• Prepare synthesis and implementation collateral.
• Collaborate with physical design teams and external implementation partners.
• Contribute to floorplanning, partitioning and implementation planning.
• Support power analysis, DFT and wider implementation activities.

Kenntnisse

ASIC implementation

STA (static timing analysis)

SDC timing constraints

UPF/low power

Linux environment

Memory macros

Third-party IP

Tools

Synthesis flows/tools

Floorplanning tools

Memory IP tooling

Jobbeschreibung

An exciting opportunity has arisen for an STA Engineer to join an innovative semiconductor company developing next-generation ASIC technology.

Working within a growing and highly technical engineering team, the STA Engineer will play an important role in preparing complex designs for physical implementation, with responsibility across timing, low power and implementation readiness. With the company continuing to grow, the role offers excellent opportunities for career progression and the potential to develop into a technical leadership position over time.

The Role Will Involve

• Developing and maintaining SDC timing constraints across internal designs and third-party IP
• Supporting static timing analysis and timing closureWorking with UPF and low power methodologies across different design partitions
• Preparing synthesis and implementation collateral
• Working closely with physical design teams and external implementation partners
• Contributing to floorplanning, partitioning and implementation planning
• Supporting power analysis, DFT and wider implementation activities

The Ideal Candidate Will Have

• Experience in ASIC implementation, STA or a closely related discipline
• Strong knowledge of SDC and static timing analysis
• Experience with synthesis and front-end implementation flows
• Practical understanding of UPF and low power design
• Experience working with SRAMs, memory macros and third-party IP
• Good understanding of physical design and floorplanning
• Previous tapeout experience would be advantageous
• Experience working in a Linux environment

All candidates must have the right to work in the Netherlands