STA Engineer

Intellectual Capital Resources Ltd; Noord-Brabant; On-site; EUR 60,000 - 90,000; Full time

Job summary

Intellectual Capital Resources Ltd in the Netherlands is seeking an experienced STA Engineer to drive timing, power and implementation readiness for next-generation ASIC designs. You will join a highly technical engineering team and contribute across timing, low power and implementation readiness, with strong opportunities for career progression.

The role involves developing and maintaining SDC timing constraints, supporting static timing analysis, working with UPF and low power methodologies,

Qualifications

• Experience in ASIC implementation/STA or closely related discipline.
• Strong knowledge of SDC and static timing analysis.
• Experience with synthesis and front-end implementation flows.
• Understanding of UPF and low power design.
• Experience with SRAMs, memory macros and third-party IP.
• Good understanding of physical design and floorplanning.
• Previous tapeout experience is advantageous.
• Experience working in a Linux environment.

Responsibilities

• Developing and maintaining SDC timing constraints across internal designs and third-party IP.
• Supporting static timing analysis and timing closure.
• Working with UPF and low power methodologies across different design partitions.
• Preparing synthesis and implementation collateral.
• Working closely with physical design teams and external implementation partners.
• Contributing to floorplanning, partitioning and implementation planning.
• Supporting power analysis, DFT and wider implementation activities.

Skills

SDC timing

Static timing analysis

UPF

Low power design

Synthesis flows

Tapeout experience

Linux environment

Job description

An exciting opportunity has arisen for an STA Engineer to join an innovative semiconductor company developing next-generation ASIC technology. Working within a growing and highly technical engineering team, the STA Engineer will play an important role in preparing complex designs for physical implementation, with responsibility across timing, low power and implementation readiness. With the company continuing to grow, the role offers excellent opportunities for career progression and the potential to develop into a technical leadership position over time.

The role will involve:

• Developing and maintaining SDC timing constraints across internal designs and third-party IP
• Supporting static timing analysis and timing closure
• Working with UPF and low power methodologies across different design partitions
• Preparing synthesis and implementation collateral
• Working closely with physical design teams and external implementation partners
• Contributing to floorplanning, partitioning and implementation planning
• Supporting power analysis, DFT and wider implementation activities

The ideal candidate will have:

• Experience in ASIC implementation, STA or a closely related discipline
• Strong knowledge of SDC and static timing analysis
• Experience with synthesis and front-end implementation flows
• Practical understanding of UPF and low power design
• Experience working with SRAMs, memory macros and third-party IP
• Good understanding of physical design and floorplanning
• Previous tapeout experience would be advantageous
• Experience working in a Linux environment

All candidates must have the right to work in the Netherlands