Sr Application Engineer – Sign-Off

Cadence; Penang; On-site; MYR 90,000 - 130,000; Full time

Job summary

Cadence in Penang seeks an Application Engineer to drive adoption of its digital implementation, physical design and verification solutions across regional customers. You will blend hands-on design expertise with technical leadership and customer engagement to optimize PPA and ensure tapeouts.

You will collaborate with RTL teams and Cadence R&D, contributing to next-generation flows and successful project execution for challenging low-power, high-speed designs at advanced nodes.

Qualifications

• BS/MS in EE/CS with 3+ years of hands‑on experience in physical design and verification.
• Experienced with ASIC design flow, static timing analysis, EM/ IR anlysis
• Prior knowledge on Timing and IR drop closure in 3DIC technologies would be an added advanrage
• Able to assume responsibility for a variety of technical tasks and to work independently
• Able to be hands‑on at all levels of design, with the ability to verify, test, and characterize own designs
• Self‑motivated, able to work as a team player, and good English communication skills

Responsibilities

• The candidate will perform the iming closure, power/signal integrity signoff and EM/IR signoff
• The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed designs at the latest technology nodes.
• The responsibility of the candidate includes participating in or leading next generation physical design, methodology and flow development.
• The candidate will work closely with RTL design team to ensure successful tapeouts.

Skills

Physical design

Verification

Static timing analysis

EM/IR analysis

3DIC knowledge

English communication

Education

BS/MS in EE/CS

Tools

ASIC design flow

STA tools

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Overview

We are seeking an application Engineer to support and drive the adoption of Cadence’s digital implementation, physical design, and static verification solutions across key customers in the region.

In this role, you will combine deep hands‑on physical design expertise with technical leadership and customer engagement, helping customers achieve optimal performance, power, and area (PPA) on advanced technology nodes. You will work closely with customer design teams, Cadence R&D, Product Engineering influencing methodologies and ensuring successful project execution and tool adoption.

• The candidate will perform the iming closure, power/signal integrity signoff and EM/IR signoff
• The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed designs at the latest technology nodes.
• The responsibility of the candidate includes participating in or leading next generation physical design, methodology and flow development.
• The candidate will work closely with RTL design team to ensure successful tapeouts.

Requirement

• BS/MS in EE/CS with 3+ years of hands‑on experience in physical design and verification.
• Experienced with ASIC design flow, static timing analysis, EM/ IR anlysis
• Prior knowledge on Timing and IR drop closure in 3DIC technologies would be an added advanrage
• Able to assume responsibility for a variety of technical tasks and to work independently
• Able to be hands‑on at all levels of design, with the ability to verify, test, and characterize own designs
• Self‑motivated, able to work as a team player, and good English communication skills

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