Senior Physical Design & Verification Engineer

Cadence Design Systems; Kuala Lumpur; On-site; MYR 60,000 - 90,000; Full time

Job summary

Cadence Design Systems is seeking an Application Engineer to support and drive adoption of digital implementation, physical design, and static verification solutions in the region. You will combine hands-on physical design expertise with technical leadership and customer engagement to achieve optimal PPA on advanced nodes.

Responsibilities include timing closure, SI/EM/IR signoff, and working with RTL teams toward successful tapeouts, including exploration of next-gen methodologies and flows.

Qualifications

• BS/MS in EE/CS with 3+ years hands-on experience in physical design and verification.
• Experienced with ASIC design flow, static timing analysis, EM/IR analysis.
• 3DIC technologies knowledge is an added advantage.
• Able to work independently and as part of a team, with good English communication.

Responsibilities

• Perform timing closure, power/signal integrity signoff, and EM/IR signoff.
• Work on challenging designs including low power and high speed at latest technology nodes.
• Lead or participate in next-generation physical design, methodology, and flow development.
• Collaborate with RTL design teams to ensure successful tapeouts.

Skills

ASIC design flow

Static timing analysis

EM/IR analysis

English communication

Education

BS/MS in EE/CS

Job description

Cadence Design Systems is seeking an Application Engineer to support and drive adoption of digital implementation, physical design, and static verification solutions in the region. You will combine hands-on physical design expertise with technical leadership and customer engagement to achieve optimal PPA on advanced nodes.

Responsibilities include timing closure, SI/EM/IR signoff, and working with RTL teams toward successful tapeouts, including exploration of next-gen methodologies and flows.