Sr Application Engineer – Sign-Off

Cadence Design Systems; George Town; On-site; MYR 120,000 - 180,000; Full time

Job summary

Cadence Design Systems in Penang, Malaysia seeks an Application Engineer to support adoption of digital implementation, physical design and static verification solutions. You will combine hands-on physical design expertise with leadership and customer engagement to optimize performance, power and area on advanced nodes.

The role involves leading timing closure, EM/IR signoff, and working with RTL teams to ensure successful tapeouts, while advancing next-generation design methodologies and flows

Qualifications

• BS/MS in Electrical Engineering or Computer Science with 3+ years hands-on experience in physical design and verification.
• Experience with ASIC design flow, static timing analysis, EM/IR analysis.
• Strong English communication skills and ability to work with cross-functional teams.

Responsibilities

• Perform timing closure, power/IR signoff, and EM/IR signoff.
• Tackle low power and high speed designs at advanced nodes.
• Contribute to next-generation physical design methodologies and flows.
• Work closely with RTL teams to ensure successful tapeouts.

Skills

ASIC design flow

Static timing analysis

EM/IR analysis

English communication

Education

BS/MS in EE/CS

Job description

Job Overview

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are seeking an application Engineer to support and drive the adoption of Cadence’s digital implementation, physical design, and static verification solutions across key customers in the region. In this role, you will combine deep hands‑on physical design expertise with technical leadership and customer engagement, helping customers achieve optimal performance, power, and area (PPA) on advanced technology nodes. You will work closely with customer design teams, Cadence R&D, Product Engineering influencing methodologies and ensuring successful project execution and tool adoption.

Key responsibilities include:

• The candidate will perform the iming closure, power/signal integrity signoff and EM/IR signoff
• The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed designs at the latest technology nodes.
• The responsibility of the candidate includes participating in or leading next generation physical design, methodology and flow development.
• The candidate will work closely with RTL design team to ensure successful tapeouts.

Requirements

• BS/MS in EE/CS with 3+ years of hands‑on experience in physical design and verification.
• Experienced with ASIC design flow, static timing analysis, EM/ IR anlysis
• Prior knowledge on Timing and IR drop closure in 3DIC technologies would be an added advanrage
• Able to assume responsibility for a variety of technical tasks and to work independently
• Able to be hands‑on at all levels of design, with the ability to verify, test, and characterize own designs
• Self‑motivated, able to work as a team player, and good English communication skills

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.

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