Sr Application Engineer – Sign-Off

Cadence Design Systems; Kuala Lumpur; On-site; MYR 60,000 - 90,000; Full time

Job summary

Cadence Design Systems is seeking an Application Engineer to support and drive adoption of digital implementation, physical design, and static verification solutions in the region. You will combine hands-on physical design expertise with technical leadership and customer engagement to achieve optimal PPA on advanced nodes.

Responsibilities include timing closure, SI/EM/IR signoff, and working with RTL teams toward successful tapeouts, including exploration of next-gen methodologies and flows.

Qualifications

• BS/MS in EE/CS with 3+ years hands-on experience in physical design and verification.
• Experienced with ASIC design flow, static timing analysis, EM/IR analysis.
• 3DIC technologies knowledge is an added advantage.
• Able to work independently and as part of a team, with good English communication.

Responsibilities

• Perform timing closure, power/signal integrity signoff, and EM/IR signoff.
• Work on challenging designs including low power and high speed at latest technology nodes.
• Lead or participate in next-generation physical design, methodology, and flow development.
• Collaborate with RTL design teams to ensure successful tapeouts.

Skills

ASIC design flow

Static timing analysis

EM/IR analysis

English communication

Education

BS/MS in EE/CS

Job description

## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.**Job OverviewWe are seeking an application Engineer to support and drive the adoption of Cadence’s digital implementation, physical design, and static verification solutions across key customers in the region.In this role, you will combine deep hands-on physical design expertise with technical leadership and customer engagement, helping customers achieve optimal performance, power, and area (PPA) on advanced technology nodes. You will work closely with customer design teams, Cadence R&D, Product Engineering influencing methodologies and ensuring successful project execution and tool adoption.• The candidate will perform the iming closure, power/signal integrity signoff and EM/IR signoff• The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed designs at the latest technology nodes.• The responsibility of the candidate includes participating in or leading next generation physical design, methodology and flow development.• The candidate will work closely with RTL design team to ensure successful tapeouts.Requirement:• BS/MS in EE/CS with 3+ years of hands-on experience in physical design and verification.• Experienced with ASIC design flow, static timing analysis, EM/ IR anlysis• Prior knowledge on Timing and IR drop closure in 3DIC technologies would be an added advanrage• Able to assume responsibility for a variety of technical tasks and to work independently• Able to be hands-on at all levels of design, with the ability to verify, test, and characterize own designs• Self-motivated, able to work as a team player, and good English communication skills