Technical Staff Engineer - Design

Microchip Technology Inc.; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

Microchip Technology Inc. in Penang, Malaysia is seeking an experienced ASIC Design Engineer. Your role will include leading the ASIC design implementation process, documenting procedures, and interfacing with project teams.

The ideal candidate should have 8-12 years of experience in ASIC IC design and expertise in tools like Cadence Genus and Synopsys DesignCompiler. A Bachelor’s or Master’s Degree in Electrical/Electronics Engineering is required.

Qualifications

• 8-12 years of ASIC IC Design working experience.
• Expertise in design tools like Cadence Genus or Synopsys DesignCompiler.
• Familiar with advanced process nodes 7nm and below.

Responsibilities

• Lead ASIC design implementation from architectural understanding to tapeout.
• Document design implementation and compliance to corporate procedures.
• Interface with project manager and product-development teams.

Skills

ASIC design expertise

Technical guidance

Problem-solving skills

Scripting in Perl, TCL, Shell, or Python

Education

Bachelor’s / Master’s Degree in Electrical/Electronics Engineering

Tools

Cadence Genus

Synopsys DesignCompiler

Cadence Tempus

Synopsys Primetime

Job description

Job Description

• To lead technically in ASIC design implementation domain, which may include stages from design architectural understanding till timing signoff for tapeout.
• To develop and signoff IC design projects RTL2GDS implementation and flow improvement. Responsibilities include (as applicable)
  • Architectural and micro-architectural intent understanding
  • RTL design structure for effective and efficient synthesis implementation
  • Derive timing constraints from design spec, review and validate with respective designer/architect for signoff
  • Design‑For‑Test (DFT) implementation, covering basic scan insertion, compression, LOC/LOS, RAMBIST all the way to advanced handling for performance/schedule/coverage trade‑off
  • Low‑power design; starting from architectural feedback, vector‑driven synthesis/layout optimization and leakage/dynamic power control techniques
  • Provide technical guidance and review for team members in solving complex challenges, with high problem‑solving skill and critical thinking capability
  • Creating technical intellectual property such as patents and trade secrets
  • Drive for Best‑in‑Class design implementation approach/process or new design methodologies benchmarking
• To document I.C. Design implementation and work procedures
  • Capturing design implementation approach, consideration, challenges and solutions employed using corporate template documentation
  • Complete audit and checklist fill‑in, review and closure in compliance to corporate Design Control Procedures (DCP)
  • Filing issues, solution details and review confirmation in project ticketing system (PEPS) or CAD ticketing system (JIRA)
• To interface with
  • Project manager, product‑development and ATPG team on project related issues
  • CAD/TA on flow methodology

Requirements & Qualifications

• Bachelor’s / Master’s Degree in Electrical/Electronics Engineering, with 8‑12 years of ASIC IC Design working experience.
• Cadence Genus or Synopsys DesignCompiler expertise.
• Cadence Tempus or Synopsys Primetime expertise.

Added Advantages

• Exposure to 7nm and below advanced process nodes.
• Familiar with System‑Verilog foundation and coding.
• Strong scripting skills in Perl, TCL, Shell or Python.

Travel Time

0% - 25%