Senior Physical Design Engineer - Low Power & P&R

Microchip Technology Inc.; Penang; Presencial; MYR 240 000 - 420 000; Tempo integral

Resumo da oferta

Microchip Technology Inc. is seeking a Principal Physical Design engineer to lead physical design from floorplanning to GDS convergence, ensuring correct implementation with checks and verifications.

The role emphasizes establishing design methodologies, improving flows, and guiding a team toward meeting tight project schedules. You will work with P&R tools (ICC/PT, Innovus) and CAE verification tools, applying low power techniques and timing closure across power envelopes.

Qualificações

• Requires at least a BSEE with 6–10 years ASIC development experience.
• Experience bringing large blocks to timing, physical design and DRC/LVS closure.
• Strong understanding of floor planning, placement, timing closure, clock and power networks.
• Proficiency with P&R tools (Synopsys ICC/PT, Cadence Innovus).
• Excellent communication and mentoring abilities, capable of leading a team.

Responsabilidades

• Understand data flow and translate into physical design constraints for convergence.
• Strategy floor-planning options and fine-tune Place & Route to meet timing within power envelope.
• Implement Low Power physical design flows (Power-Gating, Clock-Gating, MBR).
• Perform and debug LEC to ensure design equivalence with gate-level netlist.
• Lead and mentor junior team members and improve design tool chains and flows.
• Collaborate with global project teams to meet targets and schedules.
• Drive design methodology and ensure best-in-class practices across projects.

Conhecimentos

ASIC design

Floorplanning

Place & Route

Low Power design

Scripting (TCL, PERL, Shell)

Verilog/VHDL

UNIX/Linux

Timing closure

Mentoring

Leadership

Formação académica

BEng/MEng in EE

ASIC tapeouts experience

Ferramentas

Synopsys ICC/PT

Cadence Innovus

Cadence PVS

Design Compiler

Genus

PrimeTime

Descrição da oferta de emprego

Microchip Technology Inc. is seeking a Principal Physical Design engineer to lead physical design from floorplanning to GDS convergence, ensuring correct implementation with checks and verifications.

The role emphasizes establishing design methodologies, improving flows, and guiding a team toward meeting tight project schedules. You will work with P&R tools (ICC/PT, Innovus) and CAE verification tools, applying low power techniques and timing closure across power envelopes.