Senior Physical Design Engineer - Power & Timing Expert

754 Altera Semiconductor Technology (M) Sdn. Bhd.; George Town; On-site; MYR 140,000 - 230,000; Full time

Job summary

754 Altera Semiconductor Technology (M) Sdn. Bhd. in Penang, Malaysia, seeks a Senior Physical Design Engineer to drive RTL-to-GDS design implementations for custom IP and SoC blocks.

You will lead the physical design flow, perform timing, power, and reliability analyses, and guide signoff across STA, LEC, ERC, and DRC checks. The role requires 5+ years in physical design with multiple tape-outs, hands-on HDL (VHDL/Verilog), and scripting (Perl/TCL/Python).

Qualifications

• 5+ years of relevant experience in physical design flow and EDA tools (Synthesis, PnR, STA).
• Hands-on expertise with scripting languages (Perl, TCL, Python) and HDL (VHDL/Verilog).
• Experience mentoring junior team members and charting their development.
• Strong initiative, analytical/problem-solving skills, and ability to work in a diverse team.

Responsibilities

• Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database ready for manufacturing.
• Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, STA, power distribution, and noise analysis.
• Conducts verification and signoff including formal equivalence verification, STA, reliability verification, LEC/ERC/DRC checks, and layout verification.
• Analyzes results and recommends fixes for current and future product architectures.
• Expertise in clock design, timing closure, power management, and DFT using industry standard EDA tools.

Skills

Mentoring

Analytical thinking

Team collaboration

Multitasking

Education

Bachelor's degree in computer engineering

Bachelor's degree in electronic engineering

Master's degree (preferred)

Tools

Perl

TCL

Python

VHDL

Verilog

Job description

754 Altera Semiconductor Technology (M) Sdn. Bhd. in Penang, Malaysia, seeks a Senior Physical Design Engineer to drive RTL-to-GDS design implementations for custom IP and SoC blocks.

You will lead the physical design flow, perform timing, power, and reliability analyses, and guide signoff across STA, LEC, ERC, and DRC checks. The role requires 5+ years in physical design with multiple tape-outs, hands-on HDL (VHDL/Verilog), and scripting (Perl/TCL/Python).