ASIC/SoC Physical Design Engineer - Power, Timing, PnR

XINPAL (MALAYSIA) SDN. BHD.; Bayan Lepas; On-site; MYR 67,000 - 134,000; Full time

Job summary

XinPal Malaysia is seeking a Physical Design Engineer in Bayan Lepas, Penang, to support end-to-end ASIC/SoC physical design. You will handle floorplanning, placement, CTS, routing, STA, timing closure, and PV debugging.

Collaboration with cross-functional teams is essential for successful chip implementation. The role requires Cadence Innovus experience, knowledge of low-power techniques, and a strong grasp of digital PD flow across advanced nodes (16nm–3nm).

Qualifications

• Bachelor's degree in Electrical/ Electronics/ Computer Engineering or related field.
• 1+ year of ASIC/SoC Physical Design implementation experience; entry-level candidates encouraged.
• Hands-on Cadence Innovus experience required.
• Strong understanding of digital physical design flow: floorplanning, placement, CTS, routing, timing closure, PV/PD verification.
• Experience with STA, timing constraints, and synthesis methodologies.
• Familiarity with DRC/LVS verification and debugging using Calibre or equivalent.

Responsibilities

• Execute floorplanning, placement, CTS, and routing for advanced tech nodes.
• Perform STA and drive timing closure by resolving violations.
• Develop and manage synthesis flows, timing constraints, and implementation methodologies.
• Conduct physical verification (DRC/LVS) and ECOs.
• Drive low-power design techniques and power-aware implementation.

Skills

Cadence Innovus

Place & Route

Static Timing Analysis

Synthesis flows

DRC LVS debugging

TCL scripting

Power-aware PD

Education

Bachelor's Degree in Electrical/Electronics/Computer Engineering

Tools

Calibre

Job description

XinPal Malaysia is seeking a Physical Design Engineer in Bayan Lepas, Penang, to support end-to-end ASIC/SoC physical design. You will handle floorplanning, placement, CTS, routing, STA, timing closure, and PV debugging.

Collaboration with cross-functional teams is essential for successful chip implementation. The role requires Cadence Innovus experience, knowledge of low-power techniques, and a strong grasp of digital PD flow across advanced nodes (16nm–3nm).