Senior Physical Design Engineer

Alchip Technologies; Bayan Lepas; Presencial; MYR 120 000 - 180 000; Tempo integral

Resumo da oferta

Alchip Technologies in Penang is seeking a backend IC design engineer to drive RTL-to-GDSII implementation for block-level or full-chip SoCs. You will work closely with front-end teams to ensure physical feasibility and optimize PPA for timing and congestion.

The role requires a degree in EE and hands-on experience with tapeout, Tcl/Perl scripting, and standard EDA tools. You will manage backend schedules and lead risk mitigation efforts in a fast-paced environment.

Qualificações

• Bachelor's or MS degree in EE or related field.
• Experience with top-level design and chip floorplanning.
• Familiar with Cadence EDI, Synopsys ICC flow and Mentor Calibre.

Responsabilidades

• Implement RTL-to-GDSII flow for block-level or full-chip SoCs.
• Coordinate with front-end design team to ensure design feasibility.
• Analyze backend timing, congestion, and optimize PPA from an implementation view.
• Perform sign-off tasks such as STA/IR/EM/PV, etc.
• Lead backend status tracking, identify risks, and drive risk mitigation.

Conhecimentos

Top-level design experience

Chip floorplan experience

Design automation

PPA optimization

Scripting (Tcl/Perl)

Formação académica

Bachelor's or MS in EE or related

Ferramentas

Cadence EDI

Synopsys ICC design flow

Mentor Calibre

Descrição da oferta de emprego

• Responsible for implementing RTL-to-GDSII process flow for block-level or full-chip SoCs.
• Communicate closely with the front-end design team to ensure the physical feasibility of the design modules.
• Analyze the backend design process for timing and congestion and optimize PPA from an implementation perspective.
• Responsible for various sign-off tasks, such as STA/IR/EM/PV, etc.
• Manage and track the backend status of team members, identify risks, provide effective solutions, and drive risk elimination.

Job Requirement

• Bachelor or MS Degree in EE or related disciplines
• Experience of working on top level design with chip level floor plan
• Familiar with Cadence EDI, Synopsys ICC design flow and Mentor Calibr
• Experience in advanced process nodes below 7nm is preferred
• Have complete experience in chip tapeout and be able to solve complex problems
• Familiar with TCL/ Perl scripting and design automation