Physical Design Manager

UST; Seberang Perai; On-site; MYR 350,000 - 520,000; Full time

Job summary

UST in Penang invites an experienced Senior Lead for Physical Design to steer the team through end-to-end PD flows, including floorplanning, placement, CTS, routing, timing closure, and physical verification.

You will optimize PPA, manage IR drop and EM, ensure signoff readiness, and collaborate with RTL, DFT, design verification, signoff, and foundry teams, while steering schedules and tape-out milestones.

Qualifications

• 10+ years in ASIC/SoC physical design with leadership experience.
• Expertise with Cadence Innovus, Synopsys ICC2, PrimeTime, Calibre.
• Experience with 7nm/5nm/3nm process nodes.

Responsibilities

• Lead and mentor the Physical Design team.
• Manage end-to-end physical design implementation: floorplanning, power planning, placement, CTS, routing, timing closure, and physical verification.
• Drive PPA optimization, IR drop/EM, signal integrity, and ECO closure.
• Collaborate with RTL, DFT, Design Verification, Signoff, and Foundry teams.
• Manage project schedules, resources, and tape-out milestones.

Skills

Leadership

People management

Communication

Collaboration

Timing closure

PPA optimization

Power integrity

Stakeholder management

Education

Bachelor's or Master's in Electrical/Electronic Engineering

Tools

Cadence Innovus

Synopsys ICC2

PrimeTime

Calibre

Job description

• Lead and mentor the Physical Design team.
• Manage end-to-end physical design implementation: floorplanning, power planning, placement, CTS, routing, timing closure, and physical verification.
• Drive PPA optimization, IR drop/EM, signal integrity, and ECO closure.
• Collaborate with RTL, DFT, Design Verification, Signoff, and Foundry teams.
• Manage project schedules, resources, and tape-out milestones.

Requirements

• Bachelor's or Master's degree in Electrical/Electronic Engineering or related field.
• 10+ years of ASIC/SoC Physical Design experience with leadership or management experience.
• Strong expertise in Cadence Innovus, Synopsys ICC2, PrimeTime, and Calibre.
• Experience with advanced process nodes (7nm/5nm/3nm).
• Strong knowledge of timing closure, power integrity, physical verification, and PPA optimization.
• Excellent leadership, communication, and stakeholder management skills.