Senior Physical Design Engineer - Power, Timing & SoC

Altera; George Town; On-site; MYR 120,000 - 180,000; Full time

Job summary

Altera in Penang, Malaysia, is seeking a seasoned Physical Design Engineer to drive RTL-to-GDS implementation for complex IP and SoC designs. You will oversee synthesis, place-and-route, clock tree synthesis, floorplanning, STA, power and noise analysis, and signoff verification across multi-domain designs.

Ideal candidates have 5+ years in physical design, experience with deep submicron nodes, and strong scripting plus HDL skills, with mentorship capability and a collaborative, cross-functional

Qualifications

• Bachelor's degree in computer engineering or electronic engineering or related field.
• 5+ years of experience in physical design; multiple tape-out experience in deep submicron nodes; extensive knowledge of physical design flow and EDA tools; signoff flows (STA/LEC/ERC/DRC).
• Proficient in Perl, TCL, Python; HDL: VHDL/Verilog.
• Experience mentoring junior team members; strong initiative and analytical skills; multitasking in diverse teams.

Responsibilities

• Perform physical design implementation of RTL to GDS to prepare manufacturing data.
• Conduct synthesis, place-and-route, clock tree synthesis, floorplanning, STA, power/clock distribution, reliability, and noise analysis.
• Conduct verification and signoff: formal equivalence verification, STA, reliability verification, power integrity, layout verification, ERC, DRC.
• Analyze results and recommend fixes; optimize design for power, frequency, and area; contribute to design methodology improvements.

Skills

Physical design

Scripting (Perl TCL Python)

HDL VHDL Verilog

Mentoring

Problem solving

Education

Bachelor's degree in computer engineering or electronic engineering

Master's degree in computer/electronic engineering (preferred)

Tools

EDA tools

Job description

Altera in Penang, Malaysia, is seeking a seasoned Physical Design Engineer to drive RTL-to-GDS implementation for complex IP and SoC designs. You will oversee synthesis, place-and-route, clock tree synthesis, floorplanning, STA, power and noise analysis, and signoff verification across multi-domain designs.

Ideal candidates have 5+ years in physical design, experience with deep submicron nodes, and strong scripting plus HDL skills, with mentorship capability and a collaborative, cross-functional