Senior Physical Design Engineer: RTL-to-GDS, Timing & Power

Altera; Penang; On-site; MYR 180,000 - 300,000; Full time

Job summary

Altera in Penang, Malaysia, seeks a Senior Physical Design Engineer to drive the full physical design flow from RTL to GDSII and to ensure manufacturability. You will handle synthesis, place-and-route, STA, clock tree synthesis, floorplanning, and sign-off while optimizing power, frequency, and die area.

You will mentor junior engineers, contribute to method development, and work across multiple clock domains in a collaborative, global environment.

Qualifications

• Bachelor’s degree in computer engineering, electronic engineering or related field.
• 5+ years of relevant experience in physical design and tape-out in deep submicron processes.
• Extensive knowledge of physical design flow and signoff (STA, LEC, ERC, DRC).
• Hands-on scripting in Perl, TCL, Python; HDL knowledge (VHDL/Verilog).
• Experience mentoring junior team members and working in diverse teams.

Responsibilities

• Perform physical design implementation from RTL to GDS to create a manufacturable design database.
• Contribute to synthesis, place-and-route, clock tree synthesis, floorplanning, STA, and power integrity analyses.
• Execute verification and signoff flows (formality, STA, ERC, DRC) and fix violations.
• Analyze results, optimize power, performance, and area; improve design methodologies and flow automation.

Skills

Verilog

VHDL

Python

Perl

TCL

Mentoring

Problem solving

Teamwork

Education

Bachelor's degree in Computer Engineering or Electronic Engineering

Master's degree in related field

Tools

EDA tools

Job description

Altera in Penang, Malaysia, seeks a Senior Physical Design Engineer to drive the full physical design flow from RTL to GDSII and to ensure manufacturability. You will handle synthesis, place-and-route, STA, clock tree synthesis, floorplanning, and sign-off while optimizing power, frequency, and die area.

You will mentor junior engineers, contribute to method development, and work across multiple clock domains in a collaborative, global environment.