Senior Physical Design Engineer

UST; Penang; On-site; MYR 120,000 - 240,000; Full time

Job summary

UST in Penang seeks an experienced Physical Design Engineer to own Place & Route, STA, PI/SI analysis, and verification for high-speed SerDes/PHY blocks in advanced FinFET processes.

You will perform full-custom analog/mixed-signal layout in a collaborative team, optimizing timing, power, and EMIR compliance while leveraging Cadence, Synopsys, and Mentor tools to deliver robust P&R data.

Qualifications

• Experience in synthesis, Place & Route, timing closure, PV, PI, PPA improvement. Proficiency with major EDA tools (Cadence, Synopsys, Mentor).
• Implementation of multimillion gate SoC designs in cutting edge process technologies (16nm,14nm and below). FinFET experience required.
• Expertise in floor planning including power grid design to meet EMIR specifications.
• Strong timing concepts, ECO generation to fix timing/noise/EMIR violations.
• Proficiency in Tcl/Perl/Shell/Python, Mentor Calibre DRC/LVS/PERC, and Apache Totem EM & IR analysis a plus.
• Familiar with mixed signal layout techniques, LEF/DEF creation, and integrating blocks into P&R database.

Responsibilities

• Responsible for all aspects of Physical design (Place & Route, STA analysis, PI/SI analysis, physical verification, DFR design and verification, DFM design and verification).
• Perform full-custom analog and mixed-signal layout for high-speed interfaces and signal integrity systems (SerDes, PHY) in deep submicron FinFET technologies.
• Collaborate in a team environment to deliver P&R data and ensure design integrity across the flow.
• Apply EMIR specifications, ECOs, and UPF-based power management in layouts and optimizations.

Skills

Synthesis

Place & Route

Timing closure

PV/PI

PPA improvement

Analog/mixed-signal layout

CMOS digital design

Python scripting

EMIR awareness

Tools

Cadence

Synopsys

Mentor tools

Calibre DRC/LVS/PERC

Apache Totem EM & IR analysis

Cadence Virtuoso

Job description

Responsible for all aspects of Physical design (Place & Route, STA analysis, PI/SI analysis, physical verification, DFR design and verification, DFM design and verification, physical design data delivery.), Full custom and its implementation in a team environment performing full-custom analog and mixed-signal layout of next generation high-speed interfaces and signal integrity systems (aka SerDes, PHY) in deep submicron FinFET technologies.

Job Requirements:

• Experienced in synthesis, Place & Route, timing closure, PV, PI, PPA improvement. etc and major EDA tools including Cadence, Synopsys, and Mentor tools.
• Implementation of multimillion gate SoC designs in cutting edge process technologies (16nm,14nm & below). Experience in Finfet technologies is a must.
• Expertise in floor planning including power grid design to meet EMIR specifications.
• Good understanding of timing concepts, Experience in Generating and Implementing ECOs to fix timing, noise, and EMIR violations.
• Experience in Tcl/Perl/Shell/Python programming, Mentor Calibre DRC/LVS/PERC, and Apache Totem EM & IR analysis is a plus.
• Familiar with mixed signal layout matching techniques, such as interdigitation, common centroid and dummies for matching, bypass capacitor design and optimization, power supply bus construction using star connections, critical route shielding, triple well layout, ESD device and cell layout, and guard ring layout methods.
• Knowledge of low-power UPF flows. Ability to create LEF and DEF of analog/custom blocks, define the pins ports for the block, integrate them into the P&R database, and maintain the hierarchy for extraction and verification. Need to be able to merge and integrate the database into the Cadence Virtuoso database.
• Good understanding of advanced semiconductor technology process and device physics. Strong in digital logic design, CMOS & strong analytical ability.
• Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment