Senior Physical Design Engineer

SIGNOFF SEMICONDUCTORS PVT. LTD.; Bayan Lepas; On-site; MYR 120,000 - 240,000; Full time

Job summary

SIGNOFF SEMICONDUCTORS PVT. LTD. in Bayan Lepas, Malaysia, seeks a Senior Physical Design Engineer to own the RTL-to-GDSII flow for complex blocks and sub-systems.

You will drive floorplanning, CTS, routing, and signoff, collaborating with RTL, STA, power and verification teams to meet PPA targets and ensure robust physical design.

Qualifications

• 4–8 years of experience in ASIC/SoC Physical Design.
• Proven experience with PD tools: Innovus, Tempus, Voltus, RedHawk, Calibre.
• Block/sub-system level integration and signoff flows.
• Understanding of STA, Physical Verification and low-power design (UPF/CPF).
• Experience with 16nm and below nodes preferred.
• Strong debugging and problem solving in timing, congestion and physical verification.

Responsibilities

• Own the physical design flow from RTL to GDSII for complex blocks/sub-systems.
• Drive floorplanning, power planning, placement, CTS, routing and signoff (timing, IR, EM, DRC/LVS).
• Coordinate with block-level PD owners for seamless subsystem integration.
• Analyze and optimize PPA to meet design targets.
• Collaborate with RTL, STA, power DFT and verification for convergence.
• Lead ECO cycles for timing, congestion and physical signoff closure.
• Review and debug physical verification and timing issues.

Skills

ASIC/SoC Physical Design

Physical design debugging

Timing analysis

Power integrity

Clock tree synthesis

Tools

Innovus

Tempus

Voltus

RedHawk

Calibre

Job description

SIGNOFF SEMICONDUCTORS PVT. LTD. | Full time

Senior Physical Design Engineer

Bayan Lepas, Malaysia

SignOff Semiconductors is a consulting company that was founded in 2015 by a group of semiconductor professionals. Since then, the company has provided design services to several companies in the semiconductor industry through continuous service partnerships. SignOff semiconductors is a fast-growing company with a deep focus on getting excellent talent from the industry as well as picking exceptional talent from the academics.

Our unique and transparent work culture has helped us to retain the best talent and we collectively deliver high quality design services. Our team has a vast experience, and we can serve our clients on various services like Physical Design, Full Custom Analog and Digital Custom Layout and Verification, RTL Design, Verification, Embedded and Firmware.

SignOff Semiconductor has offices in Bengaluru, Hyderabad, Toronto (Ontario, Canada), and California (US) in order to serve its customer based on their asks & needs.

Job Description

Ownthe physical design flow from RTL - GDSII for complex blocks/sub-systems.

Drivefloorplanning, power planning, placement, clock tree synthesis(CTS), routing and signoff (timing, IR, EM, DRC/LVS)

Coordinatewith block-level PD owners if necessary and ensure seamlessintegration at sub-system level.

Analyzeand optimize PPA (Power, Performance, Area) to meet design targets.

Collaboratewith RTL, STA, power DFT and verification for design convergence.

LeadECO cycles for timing, congestion and physical signoff closure.

Reviewand debug physical verification and timing issues.

Requirements

4-8 years of experience in ASIC/SOC Physical Design.

Strong expertise in industry standard PD tools (Innovus,Tempus, Voltus, RedHawk, Calibre)

Proven experience in block/sub-system level integration andsignoff flows.

Good understanding of STA, Physical Verification and low-powerdesign methodologies (UPF/CPF)

Hands on experience with lower process nodes (16nm and below preferred)

Strong debugging and problem solving skills in timing,congestion and physical verification

Hands on experience in handling Analog custom routes,understanding specification to meet R and C

Experience in multi-voltage, multi-frequency design

Knowledge of EM/IR-drop analysis and mitigation

Excellent communication and leadership skills