Senior Physical Design Engineer: High-Speed SerDes & FinFET

UST; Penang; On-site; MYR 120,000 - 240,000; Full time

Job summary

UST in Penang seeks an experienced Physical Design Engineer to own Place & Route, STA, PI/SI analysis, and verification for high-speed SerDes/PHY blocks in advanced FinFET processes.

You will perform full-custom analog/mixed-signal layout in a collaborative team, optimizing timing, power, and EMIR compliance while leveraging Cadence, Synopsys, and Mentor tools to deliver robust P&R data.

Qualifications

• Experience in synthesis, Place & Route, timing closure, PV, PI, PPA improvement. Proficiency with major EDA tools (Cadence, Synopsys, Mentor).
• Implementation of multimillion gate SoC designs in cutting edge process technologies (16nm,14nm and below). FinFET experience required.
• Expertise in floor planning including power grid design to meet EMIR specifications.
• Strong timing concepts, ECO generation to fix timing/noise/EMIR violations.
• Proficiency in Tcl/Perl/Shell/Python, Mentor Calibre DRC/LVS/PERC, and Apache Totem EM & IR analysis a plus.
• Familiar with mixed signal layout techniques, LEF/DEF creation, and integrating blocks into P&R database.

Responsibilities

• Responsible for all aspects of Physical design (Place & Route, STA analysis, PI/SI analysis, physical verification, DFR design and verification, DFM design and verification).
• Perform full-custom analog and mixed-signal layout for high-speed interfaces and signal integrity systems (SerDes, PHY) in deep submicron FinFET technologies.
• Collaborate in a team environment to deliver P&R data and ensure design integrity across the flow.
• Apply EMIR specifications, ECOs, and UPF-based power management in layouts and optimizations.

Skills

Synthesis

Place & Route

Timing closure

PV/PI

PPA improvement

Analog/mixed-signal layout

CMOS digital design

Python scripting

EMIR awareness

Tools

Cadence

Synopsys

Mentor tools

Calibre DRC/LVS/PERC

Apache Totem EM & IR analysis

Cadence Virtuoso

Job description

UST in Penang seeks an experienced Physical Design Engineer to own Place & Route, STA, PI/SI analysis, and verification for high-speed SerDes/PHY blocks in advanced FinFET processes.

You will perform full-custom analog/mixed-signal layout in a collaborative team, optimizing timing, power, and EMIR compliance while leveraging Cadence, Synopsys, and Mentor tools to deliver robust P&R data.