Physical Design Engineer

Pride Global; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

Pride Global is seeking a Physical Design Engineer in Penang, Malaysia to drive the Netlist-to-GDSII implementation flow for advanced nodes. Onsite, open to perm and contract, with 4+ years of ASIC PD experience.

You will perform floorplanning, power planning, placement, CTS, routing, and timing closure; address SI/IR issues; run DRC/LVS/ERC; and automate flows with Tcl/Python. Collaborative environment for high-performance ASICs.

Qualifications

• Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering.
• 4+ years of ASIC Physical Design experience.
• Strong expertise in Netlist-to-GDSII flow, STA, CTS, and P&R.
• Hands-on experience with Synopsys (ICC2, PrimeTime) or Cadence (Innovus, Tempus).
• Proficiency in Tcl and/or Python scripting.
• Experience with advanced technology nodes (7nm/5nm/3nm) is preferred.

Responsibilities

• Perform floorplanning, power planning, placement, CTS, routing and timing closure.
• Analyze and fix setup/hold violations, signal integrity, IR-drop and electromigration issues.
• Execute DRC, LVS, ERC and antenna checks to achieve signoff-quality designs.
• Develop Tcl/Perl/Python scripts to automate physical design flows.
• Collaborate with cross-functional teams to deliver high-performance, low-power ASICs.

Skills

Netlist-to-GDSII flow

STA

CTS

P&R

Tcl scripting

Python scripting

Education

Bachelor's or Master's in Electrical/Electronics/Computer Engineering

Tools

Synopsys ICC2

PrimeTime

Cadence Innovus

Tempus

Job description

Employment type : Open to Perm & Contract

Working arrangement : Onsite

Salary Range : 15-20% Increments

We are seeking a Physical Design Engineer with 4+ years of ASIC physical design experience to drive the complete Netlist-to-GDSII implementation flow for advanced technology nodes (7nm/5nm/3nm).

Key Responsibilities:

• Perform floorplanning, power planning, placement, CTS, routing, and timing closure.


• Analyze and fix setup/hold violations, signal integrity, IR-drop, and electromigration issues.


• Execute DRC, LVS, ERC, and antenna checks to achieve signoff-quality designs.


• Develop Tcl/Perl/Python scripts to automate physical design flows.


• Collaborate with cross-functional teams to deliver high-performance, low-power ASICs.

Requirements:

• Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering.


• 4+ years of ASIC Physical Design experience.


• Strong expertise in Netlist-to-GDSII flow, STA, CTS, and P&R.


• Hands-on experience with Synopsys (ICC2, PrimeTime) or Cadence (Innovus, Tempus).


• Proficiency in Tcl and/or Python scripting.


• Experience with advanced technology nodes (7nm/5nm/3nm) is preferred.