Digital PnR CAD / Design Automation Engineer

Thundersoft; George Town; On-site; MYR 120,000 - 240,000; Full time

Job summary

Thundersoft in Penang, Malaysia is seeking an experienced Digital PnR CAD / Design Automation Engineer to develop, optimize, and maintain digital physical design implementation flows for advanced ASIC/SoC products.

You will collaborate with Physical Design, STA, DFT, RTL and CAD teams to build scalable automation frameworks, improve QoR, and drive PPA, timing closure and turnaround time across 5nm/3nm-node projects.

Qualifications

• 4–9 years of ASIC physical design or CAD/design automation experience.
• Hands-on experience with PnR flows and EDA tools.
• Strong scripting skills in Tcl; Python/Perl a plus.
• Knowledge of timing, STA, ECO, and signoff processes.

Responsibilities

• Develop, validate, maintain, and support digital PnR flows for ASIC/SoC.
• Customize and optimize PnR methodologies using EDA tools.
• Develop automation scripts and frameworks (Tcl, Python, Shell).
• Improve QoR, traceability, and design health monitoring.
• Collaborate with Physical Design, STA, DFT, RTL, and CAD teams.

Skills

Digital PnR

Design Automation

Scripting (Tcl)

Python

Bug diagnosis

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Synopsys ICC2

Fusion Compiler

Cadence Innovus

PrimeTime

Formality

Job description

Digital PnR CAD / Design Automation Engineer

Employment Type: Full-time

About the Role

We are looking for experienced Digital PnR CAD / Design Automation Engineers to develop, optimize, and maintain digital physical design implementation flows for advanced ASIC/SoC products.

You will work closely with Physical Design, STA, DFT, RTL, and CAD teams to build scalable automation frameworks, improve design quality, and enhance overall implementation productivity and turnaround time.

This role is ideal for engineers with hands‑on physical design experience and a strong interest in EDA flow development, methodology optimization, and design automation.

Key Responsibilities

• Develop, validate, maintain, and support digital physical design implementation flows across advanced process nodes.
• Customize and optimize PnR methodologies using Synopsys Fusion Compiler, ICC2, PrimeTime, Formality, and/or Cadence Innovus.
• Develop and maintain automation scripts and frameworks using Tcl, Python, Perl, and Shell.
• Build reusable flow infrastructure for synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and signoff.
• Develop QoR tracking, regression testing, reporting, and design health monitoring solutions.
• Debug flow failures, EDA tool issues, runtime bottlenecks, and methodology‑related problems.
• Collaborate with implementation teams to improve PPA (Power, Performance, and Area), congestion, timing closure, and turnaround time.
• Develop and enhance MCMM timing analysis, ECO, and signoff convergence methodologies.
• Qualify new EDA tool releases and support the deployment of new implementation methodologies.
• Work with EDA vendors to investigate tool issues and evaluate new features.
• Support advanced-node implementation flows, including 5nm, 3nm, and beyond.
• Maintain flow documentation, methodology guidelines, and user training materials.

Requirements

• Bachelor's degree or above in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Typically 4–9 years of relevant experience in ASIC physical design, digital PnR, CAD, or design automation.
• Strong understanding of digital physical design implementation flows and PnR methodologies.
• Hands‑on experience with Synopsys ICC2, Fusion Compiler, or Cadence Innovus.
• Proficiency in Tcl scripting; experience with Python, Perl, Shell, or Tcsh is an advantage.
• Knowledge of timing constraints, STA, timing closure, MCMM, ECO, and physical design signoff.
• Strong troubleshooting skills in Linux/Unix environments.
• Ability to work independently and collaborate effectively with global engineering teams.
• Strong written and spoken English communication skills.

Preferred Qualifications

• Experience with advanced process nodes such as 5nm, 3nm, or below.
• Experience optimizing PPA, congestion, runtime, and implementation turnaround time.
• Familiarity with Formality or other formal equivalence checking tools.
• Experience with AI‑assisted engineering or workflow automation tools.