Senior Physical Design Engineer

UST; Bayan Lepas; On-site; MYR 120,000 - 180,000; Full time

Job summary

UST is seeking a Physical Design Engineer (PnR or STA) to drive full-custom analog and mixed-signal layout in advanced FinFET processes. You will be responsible for Place & Route, DRC/STA analysis, PI/SI, and physical verification in a team setting.

The role requires expertise in floorplanning, timing concepts, ECOs implementation, and strong scripting and EDA tool experience. You will merge data into Cadence Virtuoso databases while ensuring timetable and data integrity.

Qualifications

• Experienced in synthesis, Place & Route, timing closure, PV, PI, PPA improvement, and major EDA tools.
• Implementation of multimillion gate SoC designs in cutting edge process technologies (16nm, 14nm & below).

Responsibilities

• Owns full Physical design (Place & Route, DRC/STA analysis, PI/SI analysis) and delivers data to CAD tools.
• Optimizes floorplanning, power grid, and timing to meet EMIR constraints.
• Generates ECOs to fix timing/noise/EMIR violations and ensures ADMS hierarchy integrity.

Skills

Place & Route

Timing closure

PV/PI/Power integrity

PPA improvement

Scripting (Python/Perl/Tcl/Shell)

EMIR/DFM knowledge

EM/IR analysis tools

CMOS/digital logic

High-speed interfaces/SerDes

Team collaboration

Self-motivation

Education

Bachelor of Engineering or ME/M.Tech

Tools

Cadence

Synopsys

Mentor Graphics

Apache Totem EM & IR

Calibre DRC/LVS/PERC

Cadence Virtuoso

Job description

Physical Design Engineer (PnR or STA)

Responsible for all aspects of Physical design (Place & Route, DRC STA analysis, PI/SI analysis, physical verification, DFR design and verification, DFM design and verification, physical design data delivery.), Full custom and its implementation in a team environment performing full-custom analog and mixed-signal layout of next generation high-speed interfaces and signal integrity systems (aka SerDes, PHY) in deep submicron FinFET technologies.

Job Requirements:

• Experienced in synthesis, Place & Route, timing closure, PV, PI, PPA improvement. etc and major EDA tools including Cadence, Synopsys, and Mentor tools.
• Implementation of multimillion gate SoC designs in cutting edge process technologies (16nm,14nm & below). Experience in Finfet technologies is a must.
• Expertise in floor planning including power grid design to meet EMIR specifications.
• Good understanding of timing concepts, Experience in Generating and Implementing ECOs to fix timing, noise, and EMIR violations.
• Experience in Tcl/Perl/Shell/Python programming, Mentor Calibre DRC/LVS/PERC, and Apache Totem EM & IR analysis is a plus.
• Familiar with mixed signal layout matching techniques, such as interdigitation, common centroid and dummies for matching, bypass capacitor design and optimization, power supply bus construction using star connections, critical route shielding, triple well layout, ESD device and cell layout, and guard ring layout methods.
• Knowledge of low‑power UPF flows. Ability to create LEF and DEF of analog/custom blocks, define the pins ports for the block, integrate them into the P&R database, and maintain the hierarchy for extraction and verification. Need to be able to merge and integrate the database into the Cadence Virtuoso database.
• Good understanding of advanced semiconductor technology process and device physics. Strong in digital logic design, CMOS & strong analytical ability.
• Good learning competency, self‑motivated, and ability to work in diverse areas in a flexible and dynamic environment
• At least 6 years of relevant experience
• Bachelor of Engineering or ME/M.Tech