Senior Physical Design Engineer for SoC, PnR & STA

UST; Bayan Lepas; On-site; MYR 120,000 - 180,000; Full time

Job summary

UST is seeking a Physical Design Engineer (PnR or STA) to drive full-custom analog and mixed-signal layout in advanced FinFET processes. You will be responsible for Place & Route, DRC/STA analysis, PI/SI, and physical verification in a team setting.

The role requires expertise in floorplanning, timing concepts, ECOs implementation, and strong scripting and EDA tool experience. You will merge data into Cadence Virtuoso databases while ensuring timetable and data integrity.

Qualifications

• Experienced in synthesis, Place & Route, timing closure, PV, PI, PPA improvement, and major EDA tools.
• Implementation of multimillion gate SoC designs in cutting edge process technologies (16nm, 14nm & below).

Responsibilities

• Owns full Physical design (Place & Route, DRC/STA analysis, PI/SI analysis) and delivers data to CAD tools.
• Optimizes floorplanning, power grid, and timing to meet EMIR constraints.
• Generates ECOs to fix timing/noise/EMIR violations and ensures ADMS hierarchy integrity.

Skills

Place & Route

Timing closure

PV/PI/Power integrity

PPA improvement

Scripting (Python/Perl/Tcl/Shell)

EMIR/DFM knowledge

EM/IR analysis tools

CMOS/digital logic

High-speed interfaces/SerDes

Team collaboration

Self-motivation

Education

Bachelor of Engineering or ME/M.Tech

Tools

Cadence

Synopsys

Mentor Graphics

Apache Totem EM & IR

Calibre DRC/LVS/PERC

Cadence Virtuoso

Job description

UST is seeking a Physical Design Engineer (PnR or STA) to drive full-custom analog and mixed-signal layout in advanced FinFET processes. You will be responsible for Place & Route, DRC/STA analysis, PI/SI, and physical verification in a team setting.

The role requires expertise in floorplanning, timing concepts, ECOs implementation, and strong scripting and EDA tool experience. You will merge data into Cadence Virtuoso databases while ensuring timetable and data integrity.