Senior FPGA Verification Architect

Altera Corporation; Penang; On-site; MYR 171,160 - 299,530; Full time

Job summary

Altera Corporation is seeking a Lead Design Verification Engineer to perform functional logic verification of FPGA designs and develop verification plans, test benches, and environments to ensure strong coverage. You will execute plans, run system simulations, analyze timing and debug issues in pre-silicon stages, collaborating with architects and RTL teams.

The role involves maintaining verification infrastructure, reviewing verification strategies, and contributing to continuous improvement

Qualifications

• BS/MS/PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience.
• Experience in Pre Silicon Validation/Verification.
• Proficiency in OVM/UVM, SystemVerilog, constrained random verification methodologies.

Responsibilities

• Performs functional logic verification of an FPGA to meet specifications.
• Develops verification plans, test benches, and verification environment to ensure coverage.
• Executes verification plans and runs system simulation models to verify design.
• Collaborates with FPGA architects, RTL developers, and physical design teams.
• Maintains and improves verification infrastructure and methodology.

Skills

OVM/UVM

SystemVerilog

Constrained random verification

FPGA architecture

IP/SOC verification

Education

BS in Electrical or Computer Science Engineering

MS or PhD in Electrical or Computer Science

Job description

Altera Corporation is seeking a Lead Design Verification Engineer to perform functional logic verification of FPGA designs and develop verification plans, test benches, and environments to ensure strong coverage. You will execute plans, run system simulations, analyze timing and debug issues in pre-silicon stages, collaborating with architects and RTL teams.

The role involves maintaining verification infrastructure, reviewing verification strategies, and contributing to continuous improvement