FPGA Silicon Design Verification Engineer

754 Altera Semiconductor Technology (M) Sdn. Bhd.; George Town; On-site; MYR 120,000 - 180,000; Full time

Job summary

Altera is seeking a highly motivated FPGA Silicon Design Verification Engineer to join our hardware development team in Penang, Malaysia. You will verify FPGA IP blocks, subsystems, and SoC designs using SystemVerilog/UVM, ABV, and constrained-random methods, collaborating with RTL, firmware, and validation teams.

The role emphasizes coverage-driven verification, debugging, and readiness for tape-out and post-silicon support.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 3+ years of experience in digital design verification for FPGA or ASIC products.
• Strong expertise in SystemVerilog UVM ABV constrained-random verification methodologies.
• Solid understanding of digital design fundamentals, including Clock domain crossings (CDC), Reset synchronization, Pipelines, State machines, Memory architectures.
• Experience with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, Siemens QuestaSim.
• Experience developing verification components, scoreboards, monitors, agents, and coverage models.
• Strong debugging skills using waveform viewers and simulation tools.
• Proficiency with scripting languages such as Python, Perl, Tcl, or Shell scripting.
• Experience with version control systems such as Git.

Responsibilities

• Develop and execute comprehensive verification plans based on architecture and design specifications.
• Design, implement, and maintain reusable SystemVerilog/UVM verification environments, testbenches, sequences, and scoreboards.
• Create directed and constrained-random tests to verify FPGA designs.
• Define and track verification metrics, including functional coverage, code coverage, and assertion coverage.
• Develop SystemVerilog Assertions (SVA) to validate design behavior and identify corner-case issues.
• Perform debug and root-cause analysis of design failures using simulation, emulation, waveform analysis, and protocol analyzers.
• Collaborate closely with RTL designers, architects, and firmware teams to resolve functional and performance issues.
• Participate in design reviews, verification reviews, and project milestone assessments.
• Drive verification closure and ensure quality signoff before tape-out or FPGA release.
• Support post-silicon bring-up and validation activities as needed.
• Contribute to verification methodology improvements, automation, and regression infrastructure.

Skills

SystemVerilog

UVM

SVA

Functional Coverage

Regression Automation

Python

Perl

Tcl

Git

Education

Bachelor's or Master's in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Synopsys VCS

Cadence Xcelium

Siemens QuestaSim

Job description

Job Summary

We are seeking a highly motivated FPGA Silicon Design Verification Engineer to join our hardware development team. The successful candidate will be responsible for pre-silicon verification of FPGA IP blocks, subsystems, and SoC-level designs. This role requires expertise in modern verification methodologies, strong debugging skills, and the ability to work closely with design, architecture, firmware, and validation teams to ensure first-pass silicon success. The ideal candidate will have a solid background in SystemVerilog/UVM-based verification, functional coverage-driven verification, protocol verification, and FPGA or ASIC development flows.

Key Responsibilities

• Develop and execute comprehensive verification plans based on architecture and design specifications.
• Design, implement, and maintain reusable SystemVerilog/UVM verification environments, testbenches, sequences, and scoreboards.
• Create directed and constrained-random tests to verify FPGA designs.
• Define and track verification metrics, including functional coverage, code coverage, and assertion coverage.
• Develop SystemVerilog Assertions (SVA) to validate design behavior and identify corner-case issues.
• Perform debug and root-cause analysis of design failures using simulation, emulation, waveform analysis, and protocol analyzers.
• Collaborate closely with RTL designers, architects, and firmware teams to resolve functional and performance issues.
• Participate in design reviews, verification reviews, and project milestone assessments.
• Drive verification closure and ensure quality signoff before tape-out or FPGA release.
• Support post-silicon bring-up and validation activities as needed.
• Contribute to verification methodology improvements, automation, and regression infrastructure.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 3+ years of experience in digital design verification for FPGA or ASIC products.
• Strong expertise in SystemVerilog UVM (Universal Verification Methodology) Assertion-Based Verification (ABV) Constrained-random verification methodologies.
• Solid understanding of digital design fundamentals, including Clock domain crossings (CDC), Reset synchronization, Pipelines, State machines, Memory architectures.
• Experience with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, Siemens QuestaSim.
• Experience developing verification components, scoreboards, monitors, agents, and coverage models.
• Strong debugging skills using waveform viewers and simulation tools.
• Proficiency with scripting languages such as Python, Perl, Tcl, or Shell scripting.
• Experience with version control systems such as Git.

Preferred Qualifications

• Experience verifying FPGA-based networking, storage, compute acceleration, or high-speed interface IP.
• Knowledge of industry-standard protocols such as PCI Express (PCIe), Ethernet, AXI/AHB/APB, DDR Memory Interfaces, CXL, Serial communication protocols.
• Experience with coverage-driven verification and verification closure methodologies.
• Familiarity with formal verification tools and methodologies.
• Experience with FPGA platforms from Intel (Altera) or AMD/Xilinx.
• Experience with emulation, FPGA prototyping, or hardware acceleration environments.
• Knowledge of DFT, scan architecture, and silicon bring-up processes.
• Familiarity with CI/CD flows and automated regression systems.

Technical Skills

• SystemVerilog
• UVM
• SVA
• Functional Coverage
• Regression Automation
• Python/Perl/Tcl
• Git or equivalent version control systems

Desired Traits

• Strong analytical and problem-solving skills and attention to detail.
• Excellent communication and collaboration abilities.
• Ability to work effectively in a fast-paced development environment.
• Self-driven with a focus on quality and execution.
• Demonstrate fundamental values such as accountability, integrity, and a winning mindset.

Job Type: Regular Shift: Shift 1 (Malaysia)

Primary Location: Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

About Altera

Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.