Senior FPGA Verification Engineer - DFT/UVM for SoC

Altera; Bayan Lepas; On-site; MYR 120,000 - 180,000; Full time

Job summary

Altera in Penang is seeking a skilled Design Verification Engineer to verify DFT and test-related logic for complex SoC and IP designs on our flagship FPGAs. You will develop pre-silicon verification plans and build UVM-based testbenches, ensuring high-quality silicon through rigorous verification methodologies.

You will collaborate with DFT architects, design engineers, validation teams, and physical design to drive root-cause resolution and coverage.

Qualifications

• 5+ years of ASIC/SoC design verification experience.
• Strong expertise in SystemVerilog and UVM.
• Experience verifying DFT features such as: Scan insertion and scan compression, MBIST, LBIST, JTAG / IEEE 1149.x, Boundary scan, Test access mechanisms.
• Knowledge of assertions (SVA), constrained-random verification, and coverage-driven methodologies.

Responsibilities

• Develop and execute verification plans for DFT and test logic features, including scan, MBIST, LBIST, JTAG, boundary scan, and related infrastructures.
• Create and maintain SystemVerilog/UVM-based verification environments.
• Develop reusable verification components, sequences, scoreboards, assertions, and coverage models.
• Verify DFT architectures and test modes at IP, subsystem, and SoC levels.
• Perform functional, regression, and coverage-driven verification.
• Analyze simulation failures, debug RTL and testbench issues, and drive root cause resolution.
• Collaborate closely with DFT architects, design engineers, validation teams, and physical design teams.
• Review specifications and provide feedback on testability and verification requirements.
• Track verification metrics, functional coverage, code coverage, and regression results.

Skills

SystemVerilog

UVM

SVA

DFT Architectures

Scan/MBIST/LBIST/JTAG

Functional Coverage

Regression Automation

Python/Perl/Tcl

Git

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

VCS

Xcelium

Questa

Job description

Altera in Penang is seeking a skilled Design Verification Engineer to verify DFT and test-related logic for complex SoC and IP designs on our flagship FPGAs. You will develop pre-silicon verification plans and build UVM-based testbenches, ensuring high-quality silicon through rigorous verification methodologies.

You will collaborate with DFT architects, design engineers, validation teams, and physical design to drive root-cause resolution and coverage.