Senior FPGA DV Engineer – DFT & Test Verification

Altera; George Town; On-site; MYR 180,000 - 280,000; Full time

Job summary

Altera, based in Penang, Malaysia, is seeking an experienced Design Verification (DV) Engineer to verify DFT and test-related logic for complex SoCs on our flagship FPGAs. You will develop and execute pre-silicon verification plans, build UVM-based testbenches, and ensure silicon quality through rigorous verification methodologies.

Ideal candidates hold 5+ years of ASIC/SoC verification, strong SystemVerilog/UVM expertise, and hands-on experience with DFT features such as scan, MBIST, LBIST, and

Qualifications

• Bachelor's or Master's degree in EE/CE/CS or related field.
• 5+ years ASIC/SoC design verification experience.
• Strong SystemVerilog and UVM expertise.
• Experience with DFT features: Scan insertion, MBIST, LBIST, JTAG.
• Proficient in debugging simulations and RTL/testbench issues.

Responsibilities

• Develop and execute verification plans for DFT and test logic features.
• Create SystemVerilog/UVM-based verification environments.
• Develop reusable verification components, sequences, scoreboards, and coverage models.
• Verify DFT architectures and test modes at IP, subsystem, and SoC levels.
• Perform functional, regression, and coverage-driven verification.
• Analyze failures and drive root cause resolution.
• Collaborate with DFT architects, design engineers, validation teams, and physical design teams.
• Track verification metrics, functional coverage, code coverage, and regression results.

Skills

SystemVerilog

UVM

SVA

DFT Architectures

Scan/MBIST/LBIST/JTAG

Functional Coverage

Regression Automation

Python

Perl

Tcl

Git

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

VCS

Xcelium

Questa

Job description

Altera, based in Penang, Malaysia, is seeking an experienced Design Verification (DV) Engineer to verify DFT and test-related logic for complex SoCs on our flagship FPGAs. You will develop and execute pre-silicon verification plans, build UVM-based testbenches, and ensure silicon quality through rigorous verification methodologies.

Ideal candidates hold 5+ years of ASIC/SoC verification, strong SystemVerilog/UVM expertise, and hands-on experience with DFT features such as scan, MBIST, LBIST, and